Master sample application
Model support
Model | Supported |
ADM-XRC |  |
ADM-XRC-P |  |
ADM-XRC-II-Lite |  |
ADM-XRC-II |  |
ADM-XPL | |
ADM-XP | |
ADP-WRC-II | |
ADP-DRC-II | |
ADP-XPI | |
ADM-XRC-4LX | |
ADM-XRC-4SX | |
ADM-XRC-4FX | |
ADM-XRC-5LX | |
ADM-XRC-5T1 | |
The Master sample application demonstrates access to host memory by an FPGA using direct master cycles. It makes use of the Master sample FPGA design (Verilog, VHDL).
- The application allocates a user-space buffer, and calls ADMXRC2_SetupDMA to lock it in memory.
- It then obtains a scatter-gather map of the buffer, by calling ADMXRC2_MapDirectMaster.
- It initialises the user-space buffer to contain known data.
- The application waits for the user to enter commands:
- i meaning "initialize the user-space buffer to known data"
- q meaning "quit"
- r meaning "make the FPGA read from a specified location in the user buffer"
- s meaning "show the contents of the user-space buffer"
- w meaning "make the FPGA write specified data to specified a location in the user-space buffer"
Syntax
master [options ...]
Options
Option |
Type |
Meaning |
-card |
base 10 integer |
ID of card to open |
-index |
base 10 integer |
Index of card to open |