ADM-XRC SDK 2.7.0b1 User Guide (Linux)
© Copyright 2001-2007 Alpha Data
Model | Supported |
ADM-XRC | ![]() |
ADM-XRC-P | ![]() |
ADM-XRC-II-Lite | ![]() |
ADM-XRC-II | ![]() |
ADM-XPL | ![]() |
ADM-XP | ![]() |
ADP-WRC-II | |
ADP-DRC-II | |
ADP-XPI | |
ADM-XRC-4LX | ![]() |
ADM-XRC-4SX | ![]() |
ADM-XRC-4FX | ![]() |
ADM-XRC-5LX | ![]() |
ADM-XRC-5T1 | ![]() |
$ADMXRC_SDK4/fpga/vhdl/memory
The MEMORY FPGA design demonstrates how to implement an interface to the local memory on an Alpha Data reconfigurable computing card, so that a program running on the host can access the memory. The design divides the 4MB FPGA space into a lower 2MB region for registers and an upper 2MB window for accessing the memory. A bank register selects which bank is currently being accessed, and a page register is provided so that all of a large memory bank can be accessed even though the window through which it is accessed is 2MB in size.
This example demonstrates the following:
This design currently supports 11 models in Alpha Data's range, which use a total of five different types of memory:
The FPGA space is divided into two regions:
The following registers exist in the 2MB register region, which begins at local bus address 0x0:
Bank register (BANK, local bus address 0x0) | |||
Bits | Mnemonic | Type | Function |
3:0 | BANK | R/W | Selects which bank is currently available via the memory access window at local bus address 0x200000. |
31:4 | MBZ |
Page register (PAGE, local bus address 0x4) | |||
Bits | Mnemonic | Type | Function |
12:0 | PAGE | R/W | Value that selects which 2MB page of memory is currently available via the memory access window at local bus address 0x200000. |
31:13 | MBZ |
Memory control register (MEMCTL, local bus address 0x8) | |||
Bits | Mnemonic | Type | Function |
0 | RST | R/W | While this field is 1, the entire memory subsystem is held in reset. An application should NOT attempt to access memory while
this field is 1. When 0, the memory subsystem is not held in reset. |
31:1 | MBZ |
Status register (STATUS, local bus address 0x10) This register indicates the general health of the FPGA in the form of lock flags from DLL, DCMs and PLLs as well as training flags from any self-training memory banks. |
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Bits | Mnemonic | Type | Function |
0 | LLOCK | RO | When 1, indicates that the DLL or DCM that distributes LCLK within the FPGA is locked. If, 500ms or later after configuration of the FPGA, this field is not 1, the application should consider this a fatal error. |
7:1 | MBZ | ||
15:8 | MLOCK | RO | Each bit of this field represents a DCM, DLL, PLL or memory bank. In the case of a DCM, DLL or PLL, a 1 indicates that lock has been achieved. In the case of a memory bank that is self-training, a 1 indicates that the memory bank has successfully trained itself. Depending on the model in use, not all 8 bits may be used. For the precise meaning of the bits in this field, refer to the table below describing differences between models for this design. |
31:16 | MBZ |
Status register MLOCK field (STATUS, local bus address 0x10) This table describes the STATUS.MLOCK field for each supported model. | |||
ADM-XRC | |||
Bits | Mnemonic | Type | Function |
8 | BANK01 | RO | When 1, indicates that the DLL that deskews the SSRAM clocks for memory banks 0 and 1 is locked. |
9 | BANK23 | RO | When 1, indicates that the DLL that deskews the SSRAM clocks for memory banks 2 and 3 is locked. |
15:10 | MBZ | ||
ADM-XRC-P | |||
Bits | Mnemonic | Type | Function |
8 | BANK0123 | RO | When 1, indicates that the DLL that deskews the clock for all memory banks is locked. |
15:9 | MBZ | ||
ADM-XRC-II-Lite | |||
Bits | Mnemonic | Type | Function |
8 | MCLKX2 | RO | When 1, indicates that the DCM that doubles the frequency of MCLK is locked |
9 | BANK01 | RO | When 1, indicates that the DCM that deskews the SSRAM clocks for physical banks 0 and 1 is locked. |
10 | BANK23 | RO | When 1, indicates that the DCM that deskews the SSRAM clocks for physical banks 2 and 3 is locked. |
15:11 | MBZ | ||
ADM-XRC-II | |||
Bits | Mnemonic | Type | Function |
8 | MCLKX2 | RO | When 1, indicates that the DCM that doubles the frequency of MCLK is locked |
9 | BANK01 | RO | When 1, indicates that the DCM that deskews the SSRAM clocks for physical banks 0, 1 and 2 is locked. |
10 | BANK23 | RO | When 1, indicates that the DCM that deskews the SSRAM clocks for physical banks 3, 4 and 5 is locked. |
15:11 | MBZ | ||
ADM-XPL | |||
Bits | Mnemonic | Type | Function |
8 | MEMCLK | RO | When 1, indicates that the DCM that generates the clock for the memory clock domain is locked. |
9 | BANK0 | RO | When 1, indicates that the DCM that deskews the ZBT SSRAM clock is locked. |
15:10 | MBZ | ||
ADM-XP | |||
Bits | Mnemonic | Type | Function |
8 | MEMCLK | RO | When 1, indicates that the DCM that generates the clock for the memory clock domain is locked. |
15:9 | MBZ | ||
ADM-XRC-4LX and ADM-XRC-4SX | |||
Bits | Mnemonic | Type | Function |
8 | MEMCLK | RO | When 1, indicates that the DCM that generates the clock for the memory clock domain is locked. |
9 | DESKEW | RO | When 1, indicates that the DCM that deskews the clock for the ZBT SSRAMs is locked. |
15:10 | MBZ | ||
ADM-XRC-4FX | |||
Bits | Mnemonic | Type | Function |
8 | MEMCLK | RO | When 1, indicates that the DCM that generates the clock for the memory clock domain is locked. |
9 | IDELAY | RO | When 1, indicates that the IDELAYCTRL instances are locked to the IDELAY reference clock. |
10 | BANK0 | RO | When 1, indicates that DDR-II SDRAM bank 0 has successfully trained itself. |
11 | BANK1 | RO | When 1, indicates that DDR-II SDRAM bank 1 has successfully trained itself. |
12 | BANK2 | RO | When 1, indicates that DDR-II SDRAM bank 2 has successfully trained itself. |
13 | BANK3 | RO | When 1, indicates that DDR-II SDRAM bank 3 has successfully trained itself. |
15:14 | MBZ | ||
ADM-XRC-5LX | |||
Bits | Mnemonic | Type | Function |
8 | MEMCLK | RO | When 1, indicates that the PLL that generates the clocks for the memory clock domain is locked. |
9 | REF220 | RO | When 1, indicates that the PLL that generates a 220MHz clock for the IDELAYCTRL reference clock workaround is locked. |
10 | IDELAY | RO | When 1, indicates that the IDELAYCTRL instances are locked to the IDELAY reference clock. |
11 | BANK0 | RO | When 1, indicates that DDR-II SDRAM bank 0 has successfully trained itself. |
12 | BANK1 | RO | When 1, indicates that DDR-II SDRAM bank 1 has successfully trained itself. |
13 | BANK2 | RO | When 1, indicates that DDR-II SDRAM bank 2 has successfully trained itself. |
14 | BANK3 | RO | When 1, indicates that DDR-II SDRAM bank 3 has successfully trained itself. |
15 | MBZ | ||
Status register MLOCK field (STATUS, local bus address 0x10) This table describes the STATUS.MLOCK field for each supported model. | |||
ADM-XRC-5T1 | |||
Bits | Mnemonic | Type | Function |
8 | MEMCLK | RO | When 1, indicates that the PLL that generates the clocks for the memory clock domain is locked. |
9 | REF220 | RO | When 1, indicates that the PLL that generates a 220MHz clock for the IDELAYCTRL reference clock workaround is locked. |
10 | IDELAY | RO | When 1, indicates that the IDELAYCTRL instances are locked to the IDELAY reference clock. |
11 | BANK0 | RO | When 1, indicates that DDR-II SDRAM bank 0 has successfully trained itself. |
12 | BANK1 | RO | When 1, indicates that DDR-II SDRAM bank 1 has successfully trained itself. |
15:13 | MBZ |
Errata register (ERRATA, local bus address 0x14) | |||
Bits | Mnemonic | Type | Function |
0 | REF220 | R/W | This field has no effect on models in which the target FPGA is not of the Virtex-5 family. When 1, the IDELAYCTRL reference clock is 220MHz, obtained from the 200MHz crystal oscillator using a PLL that multiplies by 11/10. When 0, the IDELAYCTRL referenec clock is the 200MHz crystal oscillator. |
31:1 | MBZ |
Memory bank mode registers (MODE0...MODE15, local bus address 0x40...0x7C) There are a total of 16 MODE registers, occupying local bus addresses 0x40 to 0x7C inclusive. The interpretation of the fields in a mode register depends upon the type of memory that the register corresponds to. |
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ZBT SSRAM | |||
Bits | Mnemonic | Type | Function |
0 | PIPELINE | R/W | When this field is 0, the memory controller expects the ZBT SSRAM to be operating in flowthrough mode. When this field is 1, the memory controller expects the ZBT SSRAM to be operating in pipelined mode. |
31:1 | MBZ | ||
DDR-II SSRAM | |||
Bits | Mnemonic | Type | Function |
0 | BLEN | R/W | When this field is 0, the memory controller expects the DDR-II SSRAM device to be a burst length 2 device. When this field is 1, the memory controller expects the DDR-II SSRAM device to be a burst length 2 or 4 device. |
1 | MBZ | ||
2 | DLLOFF | R/W | When this field is 0, the memory controller enables the DLL (delay locked loop) within the DDR-II SDRAM device (this is the normal mode of operation). When this field is 1, the memory controller disables the DLL (not recommended). |
31:3 | MBZ | ||
DDR SDRAM | |||
Bits | Mnemonic | Type | Function |
0 | REG | R/W | When this field is 0, the memory controller expects the DDR SDRAM to be unregistered. When this field is 1, the memory controller expects the DDR SDRAM to be registered. |
1 | MBZ | Reserved for implementing X4 DDR SDRAM device support (must be zero in this release of the SDK). | |
3:2 | ROWS | R/W | This field specifies the number of row address bits in the DDR SDRAM devices: 0x0 => 12 bits 0x1 => 13 bits 0x2 => 14 bits 0x3 => 15 bits |
5:4 | COLS | R/W | This field specifies the number of column address bits in the DDR SDRAM devices. The number of column address bits depends on this field and also the ROWS field, as follows: 0x0 => (#rows - 4) 0x1 => (#rows - 3) 0x2 => (#rows - 2) 0x3 => (#rows - 1) For example, if ROWS = 0x1 and COLS = 0x1, then the number of column address bits is (13 - 3) = 10. |
7:6 | BANKS | R/W | This field selects the number of bank address bits in the DDR SDRAM devices: 0x0 => no bank bits, 1 internal bank 0x1 => 1 bank bit, 2 internal banks 0x2 => 2 bank bits, 4 internal banks 0x3 => 3 bank bits, 8 internal banks |
9:8 | PBANKS | R/W | This field selects the number of physical banks (that, is the number of chip select pins) in the bank: 0x0 => 1 physical bank 0x1 => 2 physical banks 0x2 => 4 physical banks 0x3 => 8 physical banks |
31:10 | MBZ | ||
DDR-II SDRAM | |||
Bits | Mnemonic | Type | Function |
0 | REG | R/W | This field is reserved for implementing registered DDR-II SDRAM support (must be zero in this release of the SDK). |
1 | MBZ | This field is reserved for implementing X4 DDR-II SDRAM device support (must be zero in this release of the SDK). | |
3:2 | ROWS | R/W | This field specifies the number of row address bits in the DDR SDRAM devices: 0x0 => 12 bits 0x1 => 13 bits 0x2 => 14 bits 0x3 => 15 bits |
5:4 | COLS | R/W | This field specifies the number of column address bits in the DDR SDRAM devices. The number of column address bits depends on this field and also the ROWS field, as follows: 0x0 => (#rows - 4) 0x1 => (#rows - 3) 0x2 => (#rows - 2) 0x3 => (#rows - 1) For example, if ROWS = 0x1 and COLS = 0x1, then the number of column address bits is (13 - 3) = 10. |
7:6 | BANKS | R/W | This field selects the number of bank address bits in the DDR SDRAM devices: 0x0 => no bank bits, 1 internal bank 0x1 => 1 bank bit, 2 internal banks 0x2 => 2 bank bits, 4 internal banks 0x3 => 3 bank bits, 8 internal banks |
9:8 | PBANKS | R/W | This field selects the number of physical banks (that, is the number of chip select pins) in the bank: 0x0 => 1 physical bank 0x1 => 2 physical banks 0x2 => 4 physical banks 0x3 => 8 physical banks |
31:10 | MBZ |
The following is a block diagram of the memory_main module, which is not specific to any model and has been written in such a way that it expects to be wrapped up by a model-specific wrapper. It implements the local bus interface and the FPGA registers. It also contains the one and only instance of the memory_banks module.
As already mentioned, the wrapper for the module memory_main is model-specific, and is also the top-level of the design. For example, there is an an ADM-XPL-specific wrapper module in the source file xpl/memory-xpl.vhd that instantiates the one and only instance of the memory_main module and takes care of some ADM-XPL-specific details, such as inputting global clocks.
The memory_main module encloses one instance of the memory_banks module. The memory_banks module is entirely model-specific and comes in several versions, one per model. Its job is fourfold:
Taking the source file xp/memory_banks-xp.vhd as an example, the following figure shows the detail about the multiplexor labelled 'MUX' in the memory_banks module. In this case, the native word width of the ddr2sram_port and ddrsdram_port instances is 64, whereas the enclosing module, memory_main, expects 32-bit data.
The outbound datapath (i.e. when the application is reading a memory bank) works as follows:
The inbound datapath (i.e. when the application is writing a memory bank) is shown in the following figure (for the ADM-XP):
The inbound datapath assembles words of the native memory width from the 32-bit data from the enclosing memory_main module:
The final figure in this discussion shows the connections between an async_port instance and a memory controller instance, such as ddr2sram_port as in the source file xp/memory_banks-xp.vhd:
There are a number of generic signals that work in the same way regardless of the type of memory that the controller interfaces to. Additionally, there may be one or more sideband signals that are specific to a particular type of memory. In this design, these sideband signals are related to the bit fields in the MODE register that is described above. The generic memory controller signals work as follows:
For a list of the VHDL source files, refer to the appropriate XST project file, as referenced in the following table:
Model | XST script file | XST project file | UCF file |
XRC with Virtex | memory-xrc-v.scr | memory-xrc-v.prj | memory-xrc-v.ucf |
XRC with Virtex-E/-EM | memory-xrc-ve.scr | memory-xrc-ve.prj | memory-xrc-ve.ucf |
XRC-P with Virtex | memory-xrcp-v.scr | memory-xrcp-v.prj | memory-xrcp-v.ucf |
XRC-P with Virtex-E/-EM | memory-xrcp-ve.scr | memory-xrcp-ve.prj | memory-xrcp-ve.ucf |
XRC-II-Lite | memory-xrc2l-v2.scr | memory-xrc2l-v2.prj | memory-xrc2l.ucf |
XRC-II | memory-xrc2-v2.scr | memory-xrc2-v2.prj | memory-xrc2.ucf |
XPL with 2VP7 | memory-xpl-v2p.scr | memory-xpl-v2p.prj | xpl/memory-xpl-2vp7 |
XPL with 2VP20 or 2VP30 | memory-xpl-v2p.scr | memory-xpl-v2p.prj | xpl/memory-xpl-2vp20 |
XP with 2VP70 | memory-xp-v2p.scr | memory-xp-v2p.prj | memory-xp-2vp70.ucf |
XP with 2VP100 | memory-xp-v2p.scr | memory-xp-v2p.prj | memory-xp-2vp100.ucf |
XRC-4LX | memory-xrc4lx-v4lx.scr | memory-xrc4lx-v4lx.prj | memory-xrc4lx.ucf |
XRC-4SX | memory-xrc4sx-v4sx.scr | memory-xrc4sx-v4sx.prj | memory-xrc4sx.ucf |
XRC-4FX with 4VFX100 | memory-xrc4fx-v4fx.scr | memory-xrc4fx-v4fx.prj | memory-xrc4fx-4vfx100.ucf |
XRC-4FX with 4VFX140 | memory-xrc4fx-v4fx.scr | memory-xrc4fx-v4fx.prj | memory-xrc4fx-4vfx140.ucf |
XRC-5LX | memory-xrc5lx-v5lx.scr | memory-xrc5lx-v5lx.prj | memory-xrc5lx.ucf |
XRC-5T1 with V5LXT | memory-xrc5t1-v5lxt.scr | memory-xrc5t1-v5lxt.prj | memory-xrc5t1.ucf |
XRC-5T1 with V5SXT | memory-xrc5t1-v5sxt.scr | memory-xrc5t1-v5sxt.prj | memory-xrc5t1.ucf |
Project Navigator projects can be found in the projnav directory as follows:
Model | Project Navigator project file |
XRC | projnav/xrc/<device> |
XRC-P | projnav/xrcp/<device> |
XRC-II-Lite | projnav/xrc2l/<device> |
XRC-II | projnav/xrc2/<device> |
XPL | projnav/xpl/<device> |
XP | projnav/xp/<device> |
XRC-4LX | projnav/xrc4lx/<device> |
XRC-4SX | projnav/xrc4sx/<device> |
XRC-4FX | projnav/xrc4fx/<device> |
XRC-5LX | projnav/xrc5lx/<device> |
XRC-5T1 | projnav/xrc5t1/<device> |
Example Modelsim-compatible script files for simulating this design are provided. First change directory to where this design is located, and then refer to the following table for the appropriate shell commands for a particular model.
These simulations make use of behavioural memory models supplied by Micron and Hynix. These models are available from the websites of the respective vendors, but for legal reasons, Alpha Data does not supply these models with this SDK. The models in question are:
Note that simulations targetting models that use DDR-II SDRAM memory may require as much as 200 microseconds of simulated time for DLL/DCM/PLL locking and memory bank training to complete. This may result in long periods of inactivity on the local bus. Such periods of inactivity do not necesary indicate that the simulation is not working as expected. Some warnings may be emitted by memory models, DCMs, DLLs and PLLs. These relate to startup and can safely be ignored, as the design is held in reset until clocks have stabilized.
Model | Shell command |
XRC | cd xrc vsim -do "do memory-xrc.do" |
XRC-P | cd xrcp vsim -do "do memory-xrcp.do" |
XRC-II-Lite | cd xrc2l vsim -do "do memory-xrc2l.do" |
XRC-II | cd xrc2 vsim -do "do memory-xrc2.do" |
XPL | cd xpl vsim -do "do memory-xpl.do" |
XP | cd xp vsim -do "do memory-xp.do" |
XRC-4LX | cd xrc4lx vsim -do "do memory-xrc4lx.do" |
XRC-4SX | cd xrc4sx vsim -do "do memory-xrc4sx.do" |
XRC-4FX | cd xrc4fx vsim -do "do memory-xrc4fx.do" |
XRC-5LX | cd xrc5lx vsim -do "do memory-xrc5lx.do" |
XRC-5T1 | cd xrc5t1 vsim -do "do memory-xrc5t1.do" |