ADM-XRC SDK 2.5.0b1 User Guide (Linux)
© Copyright 2001-2005 Alpha Data


DLL sample Verilog FPGA design

Model support

Location

Synopsis

FPGA space usage

Source files

Project Navigator files

Model support

XRC XRC-P XRC-II-Lite XRC-II XPL XP WRC-II DRC-II XPI XRC-4LX XRC-4SX
     

Location
$ADMXRC_SDK4/fpga/verilog/dll
Synopsis

The DLL FPGA design demonstrates the clock doubling capability of Virtex DLLs and Virtex-II DCMs. The local bus clock (LCLK) is input through a clock IOB and doubled using a DLL (Virtex/-E/-EM) or DCM (Virtex-II or Virtex-IIPro). A 32-bit host-readable counter is clocked by a 2X multiple of LCLK.

FPGA Space Usage

Count register (COUNT, local bus address 0x0)
Bits Mnemonic Type Function
31:0 N R/W Number of elapsed cycles of 2X multiple of LCLK

The COUNT register returns the number of elapsed cycles of the 2X multiple of LCLK. It can be preset to a particular value by writing to it.

Source files

For a list of the Verilog source files, refer to the appropriate XST project file, as referenced in the following table:

Model XST script file XST project file UCF file
XRC with Virtex dll-xrc-v.scr dll-xrc-v.prj dll-xrc.ucf
XRC with Virtex-E dll-xrc-ve.scr dll-xrc-ve.prj dll-xrc.ucf
XRC-P with Virtex dll-xrcp-v.scr dll-xrcp-v.prj dll-xrcp.ucf
XRC-P with Virtex-E dll-xrcp-ve.scr dll-xrcp-ve.prj dll-xrcp.ucf
XRC-II-Lite dll-xrc2l-v2.scr dll-xrc2l-v2.prj dll-xrc2l.ucf
XRC-II dll-xrc2-v2.scr dll-xrc2-v2.prj dll-xrc2.ucf
XPL dll-xpl-v2p.scr dll-xpl-v2p.prj dll-xpl.ucf
XP dll-xp-v2p.scr dll-xp-v2p.prj dll-xp.ucf
WRC-II dll-wrc2-v2.scr dll-wrc2-v2.prj dll-wrc2.ucf
DRC-II dll-drc2-v2.scr dll-drc2-v2.prj dll-drc2.ucf

Project Navigator files

Project Navigator projects can be found in the projnav directory as follows:

Model Project Navigator project file
XRC projnav/xrc/<device>
XRC-P projnav/xrcp/<device>
XRC-II-Lite projnav/xrc2l/<device>
XRC-II projnav/xrc2/<device>
XPL projnav/xpl/<device>
XP projnav/xp/<device>
WRC-II projnav/wrc2/<device>
DRC-II projnav/drc2/<device>

 


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