ADM-XRC SDK 2.5.0b1 User Guide (Linux)
© Copyright 2001-2005 Alpha Data


Master sample application

Supports models:

The Master sample application demonstrates access to host memory by an FPGA using direct master cycles. It makes use of the Master sample FPGA design (Verilog, VHDL).

  1. The application allocates a user-space buffer, and calls ADMXRC2_SetupDMA to lock it in memory.
  2. It then obtains a scatter-gather map of the buffer, by calling ADMXRC2_MapDirectMaster.
  3. It initialises the user-space buffer to contain known data.
  4. The application waits for the user to enter commands:

Syntax:

master [options ...]

Options:

Option Type Meaning
-card base 10 integer ID of card to open
-index base 10 integer Index of card to open

 


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