ADM-XRC SDK 2.5.0b1 User Guide (Linux)
© Copyright 2001-2005 Alpha Data


Building the sample FPGA designs

Bitstreams for all supported combinations of design, model and device are supplied prebuilt in the bit/ directory of the SDK. This directory is to the sample FPGA designs what the bin/ directory is to the sample applications. All of the sources from which the bitstreams were built are supplied in the fpga/ directory, so these bitstreams can be rebuilt from sources if necessary. Note that after rebuilding a particular bitstream, it will not automatically be picked up by the sample applications; the bitstream must be manually copied to the appropriate directory, namely bit/<design>/ relative to the root directory of the SDK. If built using Xilinx Project Navigator, the bitstream must be renamed to the form <design>-<model>-<device>.bit

For serious work, it is recommended that the user set up his own directory structure and naming convention for bitstreams in order to avoid the need to copy files.

The ADM-XRC SDK provides several ways to build the sample FPGA designs:

  1. Using Xilinx Project Navigator

    Xilinx Project Navigator projects are provided for all supported <design>-<model>-<device> combinations. Simply change to the appropriate directory and open the .npl file with ISE. The following examples illustrate where the project files are located:

    Language Design For model Device Project file and rebuilt bitstream located at...
    Verilog DLL ADM-XRC-II-Lite 2V1000 fpga/verilog/dll/projnav/xrc2l/2v1000/
    VHDL Simple ADM-XRC-II 2V3000 fpga/vhdl/simple/projnav/xrc2/2v3000/

  2. Note that Xilinx Project Navigator generally gives the bitstreams it generates the same filename as the top-level entity in the project, but with a .BIT extension. In order to use the rebuilt bitstream with the example applications, it must be copied to the bit/<design>/ directory and renamed to the form <design>-<model>-<device>.bit.

  3. Using a Makefile to build all Verilog and VHDL bitstreams

    A Makefile in the fpga/ directory is provided for building all of the bitstreams in the SDK, in both Verilog and VHDL versions. Since this generates hundreds of bitstreams, the runtime may be several hours. The following commands would rebuild all of the bitstreams in the SDK:

    $ cd $ADMXRC_SDK4/fpga
    $ make clean all
    
  4. Using a Makefile to build all Verilog or all VHDL bitstreams

    A Makefile in each of the fpga/verilog/ and fpga/vhdl/ directories is provided for building all of the bitstreams from either Verilog or VHDL source. Since this generates hundreds of bitstreams, the runtime may be several hours. The following commands would rebuild all of the Verilog bitstreams:

    $ cd $ADMXRC_SDK4/fpga/verilog
    $ make clean all
    

    The following commands would rebuild all of the VHDL bitstreams:

    $ cd $ADMXRC_SDK4/fpga/vhdl
    $ make clean all
    
  5. Using a Makefile to build all bitstreams for a particular design

    A Makefile in each design directory (fpga/verilog/<design> or fpga/vhdl/<design>) is provided for building all of the bitstreams for a particular design. Since dozens of bitstreams may be generated, the runtime may be lengthy. The following commands would rebuild all of the bitstreams for the Simple VHDL design:

    $ cd $ADMXRC_SDK4/fpga/vhdl/simple
    $ make clean all
    
  6. Using a Makefile to build invidual bitstreams

    The Makefile in each design directory may also be used to build a bitstream specifically for a certain design-target-device combination. For example, the following commands would build the Verilog version of the ZBT design for an ADM-XRC-II fitted with a 2V6000 device:

    $ cd $ADMXRC_SDK4/fpga/verilog/zbt
    $ make bit_xrc2_2v6000
    

    The full path and filename of bitstreams built this way will be (relative to the root directory of the SDK):

 


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