ADM-XRC SDK 2.5.0 User Guide (Linux)
© Copyright 2001-2005 Alpha Data
This section describes the PLXDSSM state machine that is used in most of the sample FPGA designs. It is used as a building block in the implementation of a local bus interface that responds to Direct Slave transfers.
PLXDSSM can be visualized as the following module:
The upper section of the module shows general signals such as clock, asynchronous reset and synchronous reset (either or both types of reset may be used). Below those, on the left hand section of the module, are the local bus signals, possibly qualified in some manner which is discussed below. The signals on the right hand are signals to and from the application logic. The functions of the signals are as follows:
Signal | Direction | Description |
clk | IN | This signal is the local bus clock. |
reset | IN | Asynchronous reset; if used, should be derived from the local bus reset signal LRESET#. |
sr | IN | Synchronous reset; if used, should be derived from the local bus reset signal LRESET#. |
qlads | IN | This signal must be a suitably qualified active-high version of the local bus address strobe LADS#. Typically obtained from a combinatorial function such asqlads <= !LADS# and !LA[23] and !FHOLDA |
lblast | IN | This signal should simply be an active-high version of the local bus LBLAST# signal. |
lwrite | IN | This signal should simply be the local bus LWRITE signal. |
lready | OUT | This signal should normally be converted to active-low and driven onto the local bus as LREADY# when lready_oe is asserted. |
lready_oe | OUT | This signal is the active-high output enable for the local bus LREADY# signal. |
lbterm | OUT | This signal should normally be converted to active-low and driven onto the local bus as LREADY# when lbterm_oe is asserted. |
lbterm_oe | OUT | This signal is the active-high output enable for the local bus LBTERM# signal. |
ld_oe | OUT | When this active-high signal is asserted, the user application should drive the local data bus, which is LD on models with a nonmultiplexed local bus and LAD on models with a multiplexed local bus. |
ready | IN | This signal informs the PLXDSSM module that the user application is ready to transfer data. Asserting ready causes lready to be asserted on the next cycle, assuming that a Direct Slave transfer is in progress. |
stop | IN | This signal informs the PLXDSSM module that the user application wishes to terminate the current transfer. Assuming that a Direct Slave transfer is in progress, asserting stop may or may not cause lbterm to be asserted on the next cycle, depending on whether or not ready has already been asserted. |
decode | OUT | This signal indicates that a new Direct Slave transfer has started, and that the user application should perform address decoding based upon a registered version of the local bus address. It is a single cycle pulse that occurs one cycle after qlads is asserted. decode also indicates that PLXDSSM is now sensitive to the ready and stop signals. |
write | OUT | This signal indicates whether the current Direct Slave transfer is a read (0) or a write (1). It changes only on cycles when qlads is asserted. |
transfer | OUT | This signal indicates that data is being transferred in the current cycle, and mirrors lready. Clock enables for data registers are typically derived from this signal. |
Further explanation of the relationship between the ready, stop, lready and lbterm signals is warranted. The following rules govern their behavior:
It follows from these rules that when using PLXDSSM, LREADY# cannot be asserted and then deasserted in the middle of a transfer - the proper way to make the local bus master wait is to terminate the burst, rather than attempt to hold it off by deasserting LREADY#. In some applications, this has the advantage of giving other local bus masters a chance to utilise the bus instead of wasting cycles, increasing bus efficiency.
In very simple applications, ready and stop may simply be tied high, so that the application never permits bursting on the local bus and all local bus transfers last for exactly 3 clock cycles.
The PLXDSSM module is best implemented as a state machine, and the actual implementation in this SDK is a hybrid of the Mealy and Moore implementation styles:
Thus, lbterm, ld_oe, lready_oe, stopping and write are generated Mealy-style, while decode, lready and transfer are generated Moore-style.
A couple of points should be noted about this implementation:
Here, a read and a write are shown. In the case of the write, ready is used to insert two extra wait cycles:
Notes:
Here, a burst read is shown. ready is used to insert one extra wait cycle, and stop is asserted sometime after ready in order to terminate the burst.
Notes: