DMA sample application
Supports models:
- ADM-XRC
- ADM-XRC-P
- ADM-XRCII-Lite
- ADM-XRCII
- ADM-XRCIIPro-Lite
- ADM-XRCIIPro
- ADP-WRCII
- ADP-DRCII
The DMA sample application demonstrates demand mode DMA, using the DDMA sample FPGA design (Verilog, VHDL). Also demonstrated is fast configuration of the FPGA, using DMA. The application works as follows:
- Loads the DDMA bitstream into the FPGA, using a DMA transfer.
- Creates two DMA buffers:
- One for the 'send' direction (host-to-FPGA)
- One for the receive direction (FPGA-to-host)
- Creates a 'sender' thread, which performs demand-mode DMA transfers from the host to the FPGA, using the host-to-FPGA DMA buffer.
- Creates a 'receiver' thread, which performs demand-mode DMA transfers from the FPGA to the host, using the FPGA-to-host DMA buffer.
- The DDMA FPGA design simply performs a loopback operation, placing data from the send thread in a FIFO, to be read out by the receiver thread. The receiver thread checks the data received for correctness.
- The application runs until the user enters 'q', at which point the application terminates the sender and receiver threads and frees the DMA buffers.
Syntax:
dma [options ...]
Options:
Option |
Type |
Meaning |
-card |
base 10 integer |
ID of card to open |
-index |
base 10 integer |
Index of card to open |
-lclk |
real number |
Local bus clock frequency to use, in MHz (default 33.0) |
-size |
base 10 integer |
Size of data blocks to transfer, in bytes; must be a multiple of 4 (default 65536) |
-64 |
|
Operate local bus in 32 bit mode (default) |
+64 |
|
Operate local bus in 64 bit mode |