ADM-XRC SDK 2.4.0 User Guide (Linux)
© Copyright 2001-2004 Alpha Data
Supports models:
The Simple sample application demonstrates how to implement registers in the FPGA that are accessible from the host using direct slave cycles.
The user enters hexadecimal values, which the application writes to a register in the FPGA. The application reads the values back from the FPGA and displays them. However, the FPGA nibble-reverses the values before returning them.
Normally, this application uses the Simple sample FPGA design (Verilog, VHDL). However, if the +64 option is specified on the command line, the Simple64 sample FPGA design (Verilog, VHDL) is used instead. It is important to note that when the 64-bit version is used, the application does nothing different apart from configuring the FPGA local bus space to operate in 64-bit mode (see ADMXRC2_SetSpaceConfig).
Syntax:
simple [options ...]
Options:
Option | Type | Meaning |
-card | base 10 integer | ID of card to open |
-index | base 10 integer | Index of card to open |
-64 | Operate local bus in 32 bit mode (default) | |
+64 | Operate local bus in 64 bit mode |