ADM-XRC SDK 2.4.0 User Guide (Linux)
© Copyright 2001-2004 Alpha Data
Supports models:
The FrontIO sample application uses the FrontIO sample design (Verilog, VHDL) to output a walking '1' bit on the front panel I/O connector. As soon as the bitstream has been loaded, the application exits.
Syntax:
frontio [options ...]
Options:
Option | Type | Meaning |
-card | base 10 integer | ID of card to open |
-index | base 10 integer | Index of card to open |