ADM-XRC SDK 2.3.0 User Guide (Linux)
© Copyright 2001-2003 Alpha Data


Synthesizing the sample Verilog FPGA designs

The SDK sample designs have been tested with Xilinx Synthesis Technology (4.2i + SP3). Full support for other synthesis tools is outside the scope of this SDK, but users should consult the following for information about known issues:

Each of the sample FPGA designs consists of one or more Verilog source files. There is one project (.PRJ) file per supported design-target-architecture combination. The project file, although given a .PRJ extension, is in fact a Verilog file that simply includes the required source files via the `include directive. Alternatively, the source files required for each design can be found here.

To rebuild the netlists for the sample FPGA designs, follow this producedure:

  1. Start a command prompt and change directory to the design you wish to synthesize; for example:
    cd %ADMXRC_SDK4%\fpga\verilog\simple
    
  2. Run XST in script mode, issuing one or more of the following commands:
    xst -ifn simple-xrc-v.scr
    xst -ifn simple-xrc-ve.scr
    xst -ifn simple-xrcp-v.scr
    xst -ifn simple-xrcp-ve.scr
    xst -ifn simple-xrc2l-v2.scr
    xst -ifn simple-xrc2-v2.scr
    

For each supported design-target-architecture combination, there is one XST script (.SCR) file. For example, the script for building SIMPLE targetting an ADM-XRC with a Virtex device is named simple-xrc-v. The scripts reference the project (.PRJ) files in order to pull in the necessary Verilog source files.