ADM-XRC SDK 2.3.0 User Guide (Linux)
© Copyright 2001-2003 Alpha Data
Simple sample application
Supports models:
The Simple sample application demonstrates how to implement registers in the FPGA that are accessible from the host using direct slave cycles. It makes use of the Simple sample FPGA design (Verilog, VHDL).
The user enters hexadecimal values, which the application writes to a register in the FPGA. The application reads the values back from the FPGA and displays them. However, the FPGA nibble-reverses the values before returning them.
Syntax:
simple [options ...]
Options:
Option | Type | Meaning |
-card | base 10 integer | ID of card to open |
-index | base 10 integer | Index of card to open |