ADM-XRC SDK 2.3.0 User Guide (Linux)
© Copyright 2001-2003 Alpha Data


Sample Verilog FPGA design structure

The sample Verilog FPGA designs are located in the fpga/verilog directory of the SDK. The figure below illustrates the directory structure of the SDK after installation, showing the DLL design files in detail:

Each design directory contains a number of source files plus a makefile. The makefile can be used when placing and routing a design.

The build directory for each design is initially empty. If the FPGAs are rebuilt, temporary files used during the build process are created in the this directory. Unless required for traceability or debugging purposes, these files may be deleted in order to free disk space once the build process is complete.

The edif directory for each design initially contains pre-synthesized netlists for each board/FPGA-architecture combination. The makefile in each design directory expects to find netlists here.

The output directory for each design is initially empty, but contains bitstreams (files with a .BIT extension) and other output files if the the FPGA design is rebuilt. The naming convention for the bitstreams is as follows:

<design>-<board>-<device>.bit

where:

Note that the sample applications do not load .BIT files directly from the output directories of the sample designs. Instead, they load .BIT files from the SDK bit directory. For example, the DLL sample application loads its bitstreams from the bit\dll directory. After rebuilding the DLL design, the bitstreams in fpga\verilog\dll\output can be copied to the bit\dll directory. A dummy target named install is provided in the makefile for each design that will copy the regenerated .BIT files to the SDK bit directory. It can be invoked as follows:

nmake install