ADM-XRC SDK 2.3.0 User Guide (Linux)
© Copyright 2001-2003 Alpha Data


DLL sample VHDL FPGA design

VHDL source files

Source files required for supported cards

The DLL FPGA design demonstrates the clock doubling capability of Virtex DLLs and Virtex-II DCMs. The local bus clock is input through a clock IOB and doubled using a DLL (Virtex/-E/-EM) or DCM (Virtex-II or Virtex-IIPro). A 32 bit host-readable counter is clocked by the 2X clock.

Runs on

ADM-XRC, ADM-XRC-P, ADM-XRCII-Lite, ADM-XRCII, ADM-XRCIIPro-Lite

VHDL source files

Filename Description
dll\dll.vhd Top level of design (ADM-XRC, ADM-XRC-P, ADM-XRCII-Lite, ADM-XRCII only)
dll\dll-xrc2pl.vhd Top level of design (ADM-XRCIIPro-Lite only)
dll\clocks_dcm.vhd Clock generator module clocks using DCMs
dll\clocks_dll.vhd Clock generator module clocks using DLLs
common\sdkcomp.vhd Package of common components used in sample designs
common\plxdssm.vhd Direct slave state machine module plxdssm for interfacing to local bus bridge

Source files required for supported cards (top level in bold)

Card Source files UCF file
ADM-XRC common\sdkcomp.vhd
common\plxdssm.vhd
dll\clocks_dll.vhd
dll\dll.vhd
dll\dll-xrc.ucf
ADM-XRC-P common\sdkcomp.vhd
common\plxdssm.vhd
dll\clocks_dll.vhd
dll\dll.vhd
dll\dll-xrcp.ucf
ADM-XRCII-Lite common\sdkcomp.vhd
common\plxdssm.vhd
dll\clocks_dcm.vhd
dll\dll.vhd
dll\dll-xrc2l.ucf
ADM-XRCII common\sdkcomp.vhd
common\plxdssm.vhd
dll\clocks_dcm.vhd
dll\dll.vhd
dll\dll-xrc2.ucf
ADM-XRCIIPro-Lite common\sdkcomp.vhd
common\plxdssm.vhd
dll\clocks_dcm.vhd
dll\dll-xrc2pl.vhd
dll\dll-xrc2pl.ucf