ADM-XRC SDK 2.3.0 User Guide (Linux)
© Copyright 2001-2003 Alpha Data


ZBT sample Verilog FPGA design

Verilog source files

Source files required for supported cards

The ZBT FPGA design demonstrates how to implement a host interface to the SSRAM in an FPGA design. The design divides the 4MB FPGA space into a lower 2MB region for register and an upper 2MB window for accessing the SSRAM. A page register is provided so that all of the SSRAM on a card is available to the host.

This example demonstrates the following:

Although the SSRAM on an ADM-XRC series card is 18 bits or 36 bits wide per bank, the extra 2 or 4 parity bits are not used in this application. On the ADM-XRCII-Lite, two physical banks of 18 bit wide SSRAM are combined into one logical bank of 32 bit wide SSRAM to give a total of two logical banks.

The following registers exist in the 2MB register region:

Offset in FPGA space Name Purpose
0x0 (R/W) PAGE PAGE[7:0] augments LA[20:2] to provide access to all SSRAM locations
0x4 (R/W) PIPELINE PIPELINE[0] selects mode which SSRAMs operate in:
0 selects flowthrough mode
1 selects pipeline mode
0x8 (R/W) SIZE SIZE[1:0] selects number of address bits used by SSRAMs:
0x0 selects 128k word SSRAMs (17 address bits)
0x1 selects 256k word SSRAMs (18 address bits)
0x2 selects 512k word SSRAMs (19 address bits)
0x3 selects 1M word SSRAMs (20 address bits)
0x10 (RO) INFO SSRAM Information:
INFO[23:0] is maximum SSRAM size (in words) supported by bitstream
INFO[31:24] is number of physical SSRAM banks supported by bitstream
0x14 (RO) STATUS Status information:
STATUS[0] is 1 when LCLK DLL/DCM is locked
STATUS[15:1] are 1 when the corresponding SSRAM clock DLL/DCM is locked

The ZBT design supports up to 8 banks of SSRAM, but this limit could be easily extended. The SSRAM banks are mapped in a non-interleaved manner into the augmented address space formed by PAGE[7:0] and LA[20:2]. The page register provides a 2MB window onto this address space. For example, consider an ADM-XRCII card with 6 banks of 512k by 36 SSRAM (total of 12MB of memory), where the PAGE register is set to 3:

Runs on

ADM-XRC, ADM-XRC-P, ADM-XRCII-Lite, ADM-XRCII

Verilog source files

Filename Description
zbt\zbt-xrc.v Top level of design and wrapper for zbt_main (ADM-XRC only)
zbt\zbt-xrcp.v Top level of design and wrapper for zbt_main (ADM-XRC-P only)
zbt\zbt-xrc2l.v Top level of design and wrapper for zbt_main (ADM-XRCII-Lite only)
zbt\zbt-xrc2.v Top level of design and wrapper for zbt_main (ADM-XRCII only)
zbt\zbt_main.v Module zbt_main containing the local bus interface logic
zbt\zbt_dpins.v Module zbt_dpins for instantianting IOBUF primitives with drive strength of 16mA
zbt\zbt_port.v ZBT interface module zbt_port for pipelined or flowthrough devices
zbt\clocks_dcm2.v Dual clock generator module clocks using DCMs (Virtex-II only)
zbt\clocks_dll1.v Single clock generator module clocks using DLLs (Virtex/-E/-EM only)
zbt\clocks_dll2.v Dual generator module clocks using DLLs (Virtex/-E/-EM only)
common\xstboxes.v "Black box" declarations required for synthesis with XST
common\plxdssm.v Direct slave state machine module plxdssm for interfacing to the local bus bridge

Source files required for supported cards

Card Source files UCF file
ADM-XRC with
Virtex
common\xstboxes.v
common\plxdssm.v
zbt\clocks_dll2.v
zbt\zbt_port.v
zbt\zbt_dpins.v
zbt\zbt_main.v
zbt\zbt-xrc.v
zbt\zbt-xrc-v.ucf
ADM-XRC with
Virtex-E/-EM
common\xstboxes.v
common\plxdssm.v
zbt\clocks_dll2.v
zbt\zbt_port.v
zbt\zbt_dpins.v
zbt\zbt_main.v
zbt\zbt-xrc.v
zbt\zbt-xrc-ve.ucf
ADM-XRC-P with
Virtex
common\xstboxes.v
common\plxdssm.v
zbt\clocks_dll1.v
zbt\zbt_port.v
zbt\zbt_dpins.v
zbt\zbt_main.v
zbt\zbt-xrcp.v
zbt\zbt-xrcp-v.ucf
ADM-XRC-P with
Virtex-E/-EM
common\xstboxes.v
common\plxdssm.v
zbt\clocks_dll1.v
zbt\zbt_port.v
zbt\zbt_dpins.v
zbt\zbt_main.v
zbt\zbt-xrcp.v
zbt\zbt-xrcp-ve.ucf
ADM-XRCII-Lite with
Virtex-II
common\xstboxes.v
common\plxdssm.v
zbt\clocks_dcm2.v
zbt\zbt_port.v
zbt\zbt_dpins.v
zbt\zbt_main.v
zbt\zbt-xrc2l.v
zbt\zbt-xrc2l-v2.ucf
ADM-XRCII with
Virtex-II
common\xstboxes.v
common\plxdssm.v
zbt\clocks_dcm2.v
zbt\zbt_port.v
zbt\zbt_dpins.v
zbt\zbt_main.v
zbt\zbt-xrc2.v
zbt\zbt-xrc2-v2.ucf