ADM-XRC SDK 2.3.0 User Guide (Linux)
© Copyright 2001-2003 Alpha Data
Master sample Verilog FPGA design
Source files required for supported cards
The Master FPGA design demonstrates direct master access by the FPGA to host memory.
The design contains several registers, accessible by the host using direct slave transfers:
This design expects a 23 bit (8MB) region of local bus space to be the direct master window onto the PCI bus. Since this cannot address all of a full 32-bit PCI memory space, the top 9 bits must be supplied from a paging register. This register is the DMPBAM register in the PCI9080/PCI9656. The Master sample application shows how the host should configure the PCI9080/PCI9656 to allow the FPGA to perform direct master transfers.
Runs on
ADM-XRC, ADM-XRC-P, ADM-XRCII-Lite, ADM-XRCII, ADM-XRCIIPro-Lite
Verilog source files
Filename | Description |
master\master-xrc.v | Top level of design for ADM-XRC and ADM-XRC-P |
master\master-xrc2l.v | Top level of design for ADM-XRCII-L only |
master\master-xrc2.v | Top level of design for ADM-XRCII only |
common\xstboxes.v | "Black box" declarations required for synthesis with XST |
common\plxdmsm.v | Direct master state machine module plxdmsm for interfacing to the local bus bridge |
common\plxdssm.v | Direct slave state machine module plxdssm for interfacing to local bus bridge |
Source files required for supported cards (top level in bold)
Card | Source files | UCF file |
ADM-XRC | common\xstboxes.v common\plxdmsm.v common\plxdssm.v master\master-xrc.v |
master\master-xrc.ucf |
ADM-XRC-P | common\xstboxes.v common\plxdmsm.v common\plxdssm.v master\master-xrc.v |
master\master-xrcp.ucf |
ADM-XRCII-Lite | common\xstboxes.v common\plxdmsm.v common\plxdssm.v master\master-xrc2l.v |
master\master-xrc2l.ucf |
ADM-XRCII | common\xstboxes.v common\plxdmsm.v common\plxdssm.v master\master-xrc2.v |
master\master-xrc2.ucf |