ADM-XRC SDK 2.3.0 User Guide (Linux)
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Placing and routing sample Verilog FPGA designs
If your card is fitted with a Virtex-IIES (engineering sample) device, please refer to this note for information on how to generate a working bitstream. |
The netlist obtained from synthesizing a design should be passed to the Xilinx place and route tools. Recommended and required options to the Xilinx implementation tools such as
An additional source file is required at this stage, namely a user constraints file (.UCF file) which contains pin placement information, among other things. Because each of the boards supported by this SDK has a different pinout, a different constraints file is required for each board. In addition, because of slight differences in Xilinx nomenclature for some FPGA architectures, some designs may require one constraints file per supported board-architecture combination.
The constraints files used by the sample FPGA designs are as follows:
If the Xilinx command line tools are in your PATH, you can take advantage of the makefile in each sample FPGA directory. The makefiles expect to find netlists in a directory edif below the makefile as shown here. Running the Makefile places and routes the FPGA design for all of the supported board-device combinations. To start the place and route process, follow these steps:
cd %ADMXRC_SDK4% cd fpga\verilog\ddmaNote the use of the environment variable ADMXRC_SDK4. This may save some typing. Alternatively, one could type:
cd "C:\ADMXRC_SDK4" cd fpga\verilog\ddma
makeor
nmakeAs this will place and route the design for many board-device combinations, it may take a while to finish.