ADM-XRC SDK 2.3.0 User Guide (Linux)
© Copyright 2001-2003 Alpha Data


DLL sample Verilog FPGA design

Verilog source files

Source files required for supported cards

The DLL FPGA design demonstrates the clock doubling capability of Virtex DLLs and Virtex-II DCMs. The local bus clock is input through a clock IOB and doubled using a DLL (Virtex/-E/-EM) or DCM (Virtex-II or Virtex-IIPro). A 32 bit host-readable counter is clocked by the 2X clock.

Runs on

ADM-XRC, ADM-XRC-P, ADM-XRCII-Lite, ADM-XRCII, ADM-XRCIIPro-Lite

Verilog source files

Filename Description
dll\dll.v Top level of design (ADM-XRC, ADM-XRC-P, ADM-XRCII-Lite, ADM-XRCII only)
dll\dll-xrc2pl.v Top level of design (ADM-XRCIIPro-Lite only)
dll\clocks_dcm.v Clock generator module clocks using DCMs
dll\clocks_dll.v Clock generator module clocks using DLLs
common\xstboxes.v "Black box" declarations required for synthesis with XST
common\plxdssm.v Direct slave state machine module plxdssm for interfacing to local bus bridge

Source files required for supported cards (top level in bold)

Card Source files UCF file
ADM-XRC common\xstboxes.v
common\plxdssm.v
dll\clocks_dll.v
dll\dll.v
dll\dll-xrc.ucf
ADM-XRC-P common\xstboxes.v
common\plxdssm.v
dll\clocks_dll.v
dll\dll.v
dll\dll-xrcp.ucf
ADM-XRCII-Lite common\xstboxes.v
common\plxdssm.v
dll\clocks_dcm.v
dll\dll.v
dll\dll-xrc2l.ucf
ADM-XRCII common\xstboxes.v
common\plxdssm.v
dll\clocks_dcm.v
dll\dll.v
dll\dll-xrc2.ucf
ADM-XRCIIPro-Lite common\xstboxes.v
common\plxdssm.v
dll\clocks_dcm.v
dll\dll-xrc2pl.v
dll\dll-xrc2pl.ucf