ADM-XRC SDK 2.3.0 User Guide (Linux)
© Copyright 2001-2003 Alpha Data


Running the Xilinx tools

Tips for running the Xilinx tools

When building an FPGA bitstream that targets an ADM-XRC series card, certain options must be passed to the Xilinx tools:

Tool Bitgen Option Project Navigator Option When to apply
bitgen -g drivedone:yes This option is accessible via the "Processes for Current Source" panel:
  1. Right-click on "Generate Programming File"
  2. Select "Properties"
  3. Select "Configuration Options"
  4. Set "Configuration Pin Done" to "Active pullup"
Note: ISE 5.1i does not display this option. See tip 2 below.
Always.
bitgen -g persist:yes This option is accessible via the "Processes for Current Source" panel:
  1. Right-click on "Generate Programming File"
  2. Select "Properties"
  3. Select "Readback Options"
  4. Tick "Create Readback Data Files"
  5. Tick "Allow SelectMAP Pins to Persist"
If your application needs to access the FPGA's SelectMap port after configuration.
map -pr b This option is accessible via the "Processes for Current Source" panel:
  1. Expand "Implement Design"
  2. Right-click on "Map"
  3. In the "Map Properties" tab, set "Pack I/O Registers/Latches into IOBs" to "For Inputs and Outputs"
If flip-flops should be automatically packed into IOBs.

The SDK examples use this feature to improve IOB setup and clock-to-output delays.

Tips for running the Xilinx tools

  1. When running PAR in ISE 4.2i or later, check that PAR reports the expected number of LOC'ed IOBs. Early on during the execution of PAR, you should see a message of the form:
    Device utilization summary:
    
       Number of External GCLKIOBs         1 out of 4      25%
       Number of External IOBs            45 out of 404    11%
          Number of LOCed External IOBs   45 out of 45    100%
    
       Number of SLICEs                 2612 out of 6912   38%
    
       Number of GCLKs                     1 out of 4      25%
       Number of TBUFs                   320 out of 7104    5%
    
    Generally, "Number of LOCed External IOBs" should be 100%. If not, it implies that one or more IOBs will be placed on arbitrary pins, which may cause problems. The .PAD file, which is produced along with the routed .NCD file, can be used to find out which I/O signals do not have location constraints.
  2. The following Xilinx answer explains that Project Navigator in ISE 5.1i does not display the "Active pullup" option in the properties for "Generate Programming File":

    Answer Record #15812: 5.1i Project Navigator - The "DriveDone" startup option for Virtex-II devices is not present

    A workaround for this issue is given by the following Xilinx answer:

    Answer Record #11088: 5.1i ISE- How do I specify advanced command line options in the Project Navigator GUI? (An attribute or option is not available in the GUI)

    This answer can be summarised as follows:
    1. In Windows, create or set the environment variable XIL_PROJNAV_BITGEN_OPTION, whose value is 1.
    2. Start Project Navigator.
    3. Select "Edit->Preferences" from the Project Navigator main menu.
    4. In the "Preferences" dialog, click on the "Processes" tab.
    5. Set "Property Display Level" to "Advanced".
    6. Click "Ok" to dismiss the "Preferences" dialog.
    7. Right click on "Generate Programming File" in the "Processes for Current Source" panel.
    8. Select "Properties".
    9. Click on the "General Options" tab. You should now see a text field entitled "Other Bitgen Command Line Options".
    10. Enter "-g drivedone:yes" in the "Other Bitgen Command Line Options" field.