ADM-XRC SDK 2.3.0 User Guide (Linux)
© Copyright 2001-2003 Alpha Data


ITest sample Verilog FPGA design

Verilog source files

Source files required for supported cards

The ITest FPGA design implements logic for generating FPGA interrupts on the host. The scheme used is explained in application note AN-XRC06, which can be found in the doc directory of this SDK. The ITest sample application shows how to capture and handle FPGA interrupts on the host.

Runs on

ADM-XRC, ADM-XRC-P, ADM-XRCII-Lite, ADM-XRCII, ADM-XRCIIPro-Lite

Verilog source files

Filename Description
itest\itest.v Top level of design (ADM-XRC, ADM-XRC-P, ADM-XRCII-Lite, ADM-XRCII only)
itest\itest-xrc2pl.v Top level of design (ADM-XRCIIPro-Lite only)
common\xstboxes.v "Black box" declarations required for synthesis with XST
common\plxdssm.v Direct slave state machine module plxdssm for interfacing to local bus bridge

Source files required for supported cards (top level in bold)

Card Source files UCF file
ADM-XRC common\xstboxes.v
common\plxdssm.v
itest\itest.v
itest\itest-xrc.ucf
ADM-XRC-P common\xstboxes.v
common\plxdssm.v
itest\itest.v
itest\itest-xrcp.ucf
ADM-XRCII-Lite common\xstboxes.v
common\plxdssm.v
itest\itest.v
itest\itest-xrc2l.ucf
ADM-XRCII common\xstboxes.v
common\plxdssm.v
itest\itest.v
itest\itest-xrc2.ucf
ADM-XRCIIPro-Lite common\xstboxes.v
common\plxdssm.v
itest\itest.v
itest\itest-xrc2pl.ucf