ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data
Bitstreams for all supported combinations of design, model and device are supplied prebuilt in the bit/ directory of the SDK. This directory is to the sample FPGA designs what the bin/ directory is to the sample applications. All of the sources from which the bitstreams were built are supplied in the fpga/ directory, so these bitstreams can be rebuilt from sources if necessary. Note that after rebuilding a particular bitstream, it will not automatically be picked up by the sample applications; the bitstream must be manually copied to the appropriate directory, namely bit/<design>/ relative to the root directory of the SDK. If built using Xilinx Project Navigator, the bitstream must be renamed to the form <design>-<model>-<device>.bit
For serious work, it is recommended that the user set up his own directory structure and naming convention for bitstreams in order to avoid the need to copy files.
The ADM-XRC SDK provides several ways to build the sample FPGA designs:
ISE Project Navigator files can be generated after installation of the SDK for all supported <design>-<model>-<device> combinations. Once the project files have been generated, change to the appropriate directory and open the .ise file with Project Navigator. The following examples illustrate where the project files are located:
Language | Design | For model | Device | Project file located at... |
Verilog | DLL | ADM-XPL | 2VP20 | fpga/verilog/dll/projnav/xpl/2vp20/ |
VHDL | Simple | ADM-XRC-II | 2V3000 | fpga/vhdl/simple/projnav/xrc2/2v3000/ |
Note that Xilinx Project Navigator generally gives the bitstreams it generates the same filename as the top-level entity in the project, but with a .BIT extension. In order to use the rebuilt bitstream with the example applications, it must be copied to the bit/<design>/ directory and renamed to the form <design>-<model>-<device>.bit.
A Makefile in the fpga/ directory is provided for building all of the bitstreams in the SDK, in both Verilog and VHDL versions. Since this generates hundreds of bitstreams, the runtime may be several hours. The following commands would rebuild all of the bitstreams in the SDK:
$ cd $ADMXRC_SDK4/fpga $ make clean all
The Makefile in the fpga/vhdl/ directory is provided for building all of the VHDL bitstreams from sources. Since this generates hundreds of bitstreams, the runtime may be several hours:
$ cd $ADMXRC_SDK4/fpga/vhdl $ make clean all
The Makefile in the fpga/verilog/ directory is provided for building all of the Verilog bitstreams from sources. Since this generates hundreds of bitstreams, the runtime may be several hours:
$ cd $ADMXRC_SDK4/fpga/verilog $ make clean all
The Makefile in each design directory may be used to build all bitstreams for that design. For example, to build the bitstreams for all model-device combinations of the VHDL version of the SIMPLE design, issue the following commands:
$ cd $ADMXRC_SDK4/fpga/vhdl/simple $ make clean all
The Makefile in each design directory may also be used to build a bitstream specifically for a certain design-model-device combination. For example, the following commands would build the Verilog version of the ZBT design for an ADM-XRC-II fitted with a 2V6000 device:
$ cd $ADMXRC_SDK4/fpga/verilog/zbt $ make bit_xrc2_2v6000
The full path and filename of bitstreams built this way will be (relative to the root directory of the SDK):