ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data
The plxdssm component is part of the localbus package and provides the control mechanism for a local bus interface within an FPGA design.
Projects making use of this component must include all of the following source files (relative to root of SDK installation):
fpga/vhdl/common/localbus/localbus_pkg.vhd
fpga/vhdl/common/localbus/plxdssm.vhd
The signals of this interface to and from the user application are as follows:
Signal | Type | Function | Note |
clk | in | Local bus clock This port must be driven by the clock that drives the local bus interface of the FPGA design. |
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decode | out | Address decoding pulse This output pulses for exactly one clock cycle, in the cycle following the assertion of qlads. Typically, the address presented on the local bus by the current local bus master is captured in a register whose contents are valid in the cycle following the qlads pulse. The FPGA can use the decode pulse to as an indication that the captured local bus address is valid, so that it may perform further decoding of the address. |
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eld_oe | out | Early LD / LAD output enable This output shows the same waveform as ld_oe_l, but is active high and one cycle early compared to ld_oe_l. |
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idle | out | Interface idle This status output indicates whether or not the plxdssm module is currently handling a local bus cycle. It may be asserted for two reasons:
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lblast | in | LBLAST# in This input must be driven by an active high version of the LBLAST# signal from the local bus. |
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lbterm | in | LBTERM# in This input must be driven by an active high version of the LBTERM# signal from the local bus. |
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lbterm_o_l | out | LBTERM# out This output must drive the LBTERM# signal on the local bus whenever lbterm_oe_l is asserted. |
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lbterm_oe_l | out | LBTERM# output enable Whenever this output is asserted (logic 0), the FPGA must drive the LBTERM# pin with the current value of the lbterm_o_l output. |
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ld_oe_l | out | LD / LAD output enable This is an active low output enable signal for the LAD / LD pins. When asserted (logic 0), the LAD / LD pins should be driven by the FPGA. |
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lready_o_l | out | LREADY# out This output must drive the LREADY# signal on the local bus whenever the lready_oe_l is asserted. |
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lready_oe_l | out | LREADY# output enable Whenever this output is asserted (logic 0), the FPGA must drive the LREADY# pin with the current value of the lready_o_l output. |
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lwrite | in | LWRITE in This input must be driven by the LWRITE signal from the local bus. |
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qlads | in | Qualified address strobe This input should be pulsed for one clock cycle, when a local bus cycle begins. This signal is typically generated by qualifying the LADS# signal by simple address decoding, which may also include FHOLDA. |
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ready | in | Data ready The user application should assert this signal when it is ready to transfer data during a local bus cycle. As a result of asserting ready, the plxdssm module asserts the lready_o_l output in the next clock cycle. The ready input may be pulsed for as little as one cycle cycle; lready_o_l however remains asserted until the end of the current local bus cycle. Asserting ready also permits the plxdssm module to assert lbterm_o_l, according to the following rules given in the description for stop. | |
rst | in | Asynchronous reset This port may be driven by an asynchronous reset for the local bus interface, or tied to logic 0 (if not required). |
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sr | in | Synchronous reset This port may be driven by a synchronous reset for the local bus interface, or tied to logic 0 (if not required). |
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stop | in | Terminate local bus cycle The user application should assert this signal when it wishes to terminate the current local bus cycle. If stop is asserted, the plxdssm module may or may not assert lbterm_o_l in the next clock cycle, according to the following rules:
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transfer | out | Transfer indication This output is asserted on every clock cycle in which data is transferred on the local bus. For a bursting local bus cycle, this output may be asserted for many consecutive clock cycles. |
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write | out | Write indication This output is asserted to indicate that the current local bus cycle is a write (that is, the data is transferred from the local bus master to the local bus slave). |
In a typical FPGA design, there is exactly one instance of plxdssm. It provides the control mechanism that enables the FPGA to respond to local bus cycles, but does not provide the datapath. A typical usage scenario is presented in the following figure:
There are a couple of things to note about the above example:
qlads <= not lads_l and not fholda and not la(23)often suffices.