ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


Demand-mode DMA transfers

The DMA engines on the local bus bridge of an ADM-XRC series card are capable of operating in demand-mode. In demand-mode, instead of transferring data to or from the FPGA as fast as possible, a DMA engine will transfer data "on-demand" of the FPGA. For example, in a design which contains a FIFO whose data is read out via the local bus, the FPGA can request that the DMA engine transfer some data only when the FIFO is not empty.

To use demand-mode DMA, the host must specify demand-mode in the mode word for a DMA transfer. This is done using the ADMXRC2_BuildDMAModeWord function. The mode word that includes demand-mode can then be supplied in a call to ADMXRC2_DoDMA, for example. Demand-mode may be freely mixed with the other DMA modes, such as constant address mode and LEOT mode.

To use demand mode:

The LDREQ# and LDACK# signals actually comprise pairs of request-acknowledge signals, one pair per DMA engine in the PCI-to-local bus bridge on an ADM-XRC series card. They work as follows:

  1. Asserting a particular bit of LDREQ# requests that the corresponding DMA engine transfer some data.
  2. When the local bus bridge performs a burst in response to that request, it asserts the corresponding bit of LDACK#.
  3. The FPGA can stop the transfer, "pausing" the DMA engine, by deasserting LDREQ#. Once paused, the DMA engine will not attempt to transfer more data until the FPGA reasserts LDREQ#.

This following topics illustrate the local bus protocol when demand-mode DMA is used:

Demand-mode DMA burst read, LDREQ# kept asserted

Demand-mode DMA burst read, LDREQ# deasserted to pause transfer

Demand-mode DMA single word read, LDREQ# deasserted early

Demand-mode DMA write, LBTERM# breaks up bursts

Demand-mode DMA read, LDREQ# kept asserted

In this example, LDREQ#n is kept asserted.

Note:

  1. As long as LDREQ#n kept asserted, DMA engine n continues to generate bursts on the local bus.

Demand-mode DMA read, LDREQ# deasserted to pause transfer

In this example, LDREQ#n is deasserted mid-burst in order to "pause" the DMA transfer.

Note:

  1. This assumes that the assertion of LBLAST# was caused by deassertion of LDREQ#n, not because the DMA engine temporarily filled its FIFO.
  2. DMA engine n is "paused" at the end of the burst. It will not initiate another burst on the local bus until LDREQ#n is reasserted.

Demand-mode DMA single word read, LDREQ# deasserted early

In this example, LDREQ#n is deasserted early in order to perform a single word demand-mode DMA burst.

Note:

  1. In order to make a DMA engine perform a single word demand-mode DMA burst and then pause, LDREQ#n must be deasserted on or before the cycle in which LDACK#n is asserted.

Demand-mode DMA write, LBTERM# breaks up bursts

In this example, LBTERM# breaks up the demand-mode DMA bursts.

Note:

  1. Asserting LBTERM# does not in itself pause a DMA engine - it merely breaks up the bursts.

 


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