ADM-XRC SDK 2.8.1 User Guide (Linux)
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The ddr2sdram_timing_t datatype

The ddr2sdram_timing_t datatype is exported by the memif package, and is used to specify the timing parameters of an instance of ddr2sdram_port.

It is a record type, defined as follows:

type ddr2sdram_timing_t is
record
    t_refresh : natural; -- Average periodic refresh interval
    t_mrd     : natural; -- Minimum time between mode register set commands
    t_dllr    : natural; -- Minimum time between DLL leaving reset and first read command
    t_rp      : natural; -- Minimum time between row precharge and row activate commands
    t_rfc     : natural; -- Minimum time between refresh command and any other command
    t_act     : natural; -- Minimum time between row activate command and any read/write command
    t_wtr     : natural; -- Minimum time between write command and read command, assuming same row
    t_rtw     : natural; -- Minimum time between read command and write command, assuming same row
    t_rtp     : natural; -- Minimum time between read command and precharge command
    t_wtp     : natural; -- Minimum time between write command and precharge command
    t_ras     : natural; -- Minimum number of cycles that a row must be open
end record;

This datatype can normally treated as an abstract datatype, since the user application need typically only use one of the predefined constants of type ddr2sdram_timing_t. However, should it be necessary to create a new value, the members are defined as follows:

Member Type Function
t_refresh natural Average periodic refresh interval, in clk0 cycles.
t_mrd natural Mode register set command period, in clk0 cycles.
t_dllr natural Minimum number of clk0 cycles between DLL reset deasserted to first memory access.
t_rp natural Minimum number of clk0 cycles between PRE (precharge) and ACT (row activation) or REF (refresh) commands.
t_rfc natural Number of clk0 cycles for completion of a REF (refresh) operation.
t_act natural Minimum number of clk0 cycles between ACT (row activate) and a read or write command.
t_wtr natural Minimum number of clk0 cycles between a write and a read command.
t_rtw natural Minimum number of clk0 cycles between a read and a write command.
t_rtp natural Minimum number of clk0 cycles between a read and a PRE (precharge) command.
t_wtp natural Minimum number of clk0 cycles between a write and a PRE (precharge) command.
t_ras natural Minimum number of clk0 cycles between ACT (row activate) and PRE (precharge) command.

All values in the above table are numbers of clk0 cycles. Thus:

 


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