ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


MEMORY sample VHDL FPGA design

Model support

Location

Synopsis

FPGA space usage

Explanation of design

Source files

Project Navigator files

Modelsim scripts

Model support

ModelSupported
ADM-XRC
ADM-XRC-P
ADM-XRC-II-Lite
ADM-XRC-II
ADM-XPL
ADM-XP
ADP-WRC-II 
ADP-DRC-II 
ADP-XPI 
ADM-XRC-4LX
ADM-XRC-4SX
ADM-XRC-4FX
ADPE-XRC-4FX
ADM-XRC-5LX
ADM-XRC-5T1
ADM-XRC-5T2 / ADM-XRC-5T2-ADV
ADM-XRC-5TZ
ADM-XRC-5T-DA1

Note: the ADM-XRC-5T2-ADV version of this design uses the same source files and bitstreams as the ADM-XRC-5T2, so separate files are not included within this SDK.

Location
$ADMXRC_SDK4/fpga/vhdl/memory
Synopsis

The MEMORY FPGA design is a refernce design demonstrating how to implement an interface to the on-board memory on a reconfigurable computing card so that it is effectively dual-ported. Thus, a program running on the host can access the memory, and at the same time a "user application" block can also access the memory.

This example demonstrates the following:

This design currently supports 15 models in Alpha Data's range of reconfigurable computing cards, which use a total of five different types of memory:

FPGA Space Usage

The FPGA space is divided into two regions:

The following registers exist in the 2MB register region, which begins at local bus address 0x0:

Bank register (BANK, local bus address 0x0)
Bits Mnemonic Type Function
3:0 BANK R/W Selects which bank is currently available via the memory access window at local bus address 0x200000.
31:4   RO/MBZ (Reserved)

Page register (PAGE, local bus address 0x4)
Bits Mnemonic Type Function
12:0 PAGE R/W Value that selects which 2MB page of memory is currently available via the memory access window at local bus address 0x200000.
31:13   RO/MBZ (Reserved)

Memory control register (MEMCTL, local bus address 0x8)
Bits Mnemonic Type Function
0 RST R/W While this field is 1, the entire memory subsystem is held in reset. An application should NOT attempt to access memory while this field is 1.
When 0, the memory subsystem is not held in reset.
31:1   RO/MBZ (Reserved)

Status register (STATUS, local bus address 0x10)

This register indicates the general health of the FPGA in the form of lock flags from DLL, DCMs and PLLs as well as training flags from any self-training memory banks.
Bits Mnemonic Type Function
0 LLOCK RO When 1, indicates that the DLL or DCM that distributes LCLK within the FPGA is locked. If, 500ms or later after configuration of the FPGA, this field is not 1, the application should consider this a fatal error.
0 SLLOCK R/W1C Sticky loss of lock flag. When 1, indicates that the DLL or DCM that distributes LCLK within the FPGA has lost lock at some point. When written with 1, this field is cleared to 0.
7:2   RO/MBZ (Reserved)
15:8 MLOCK RO Each bit of this field represents a DCM, DLL or PLL. A 1 indicates that lock has been achieved. Depending on the model in use, not all 8 bits may be used. For the precise meaning of the bits in this field, refer to the table below describing differences between models for this design.
23:16 SMLOCK R/W1C Sticky loss of lock/training flags. Each bit of this field returns 1 if the corresponding DCM, DLL or PLL lost lock. Note that unused bits of this field (because there is no corresponding DCM, DLL or PLL) will always return 1.
31:24   RO/MBZ (Reserved)

Status register MLOCK field (STATUS, local bus address 0x10)

This table describes the STATUS.MLOCK field for each supported model.
ADM-XRC
Bits Mnemonic Type Function
8 BANK01 RO When 1, indicates that the DLL that deskews the SSRAM clocks for memory banks 0 and 1 is locked.
9 BANK23 RO When 1, indicates that the DLL that deskews the SSRAM clocks for memory banks 2 and 3 is locked.
15:10   RO/MBZ (Reserved)
ADM-XRC-P
Bits Mnemonic Type Function
8 BANK0123 RO When 1, indicates that the DLL that deskews the clock for all memory banks is locked.
15:9   RO/MBZ (Reserved)
ADM-XRC-II-Lite
Bits Mnemonic Type Function
8 MCLKX2 RO When 1, indicates that the DCM that doubles the frequency of MCLK is locked
9 BANK01 RO When 1, indicates that the DCM that deskews the SSRAM clocks for physical banks 0 and 1 is locked.
10 BANK23 RO When 1, indicates that the DCM that deskews the SSRAM clocks for physical banks 2 and 3 is locked.
15:11   RO/MBZ (Reserved)
ADM-XRC-II
Bits Mnemonic Type Function
8 MCLKX2 RO When 1, indicates that the DCM that doubles the frequency of MCLK is locked
9 BANK01 RO When 1, indicates that the DCM that deskews the SSRAM clocks for physical banks 0, 1 and 2 is locked.
10 BANK23 RO When 1, indicates that the DCM that deskews the SSRAM clocks for physical banks 3, 4 and 5 is locked.
15:11   RO/MBZ (Reserved)
ADM-XPL
Bits Mnemonic Type Function
8 MEMCLK RO When 1, indicates that the DCM that generates the clock for the memory clock domain is locked.
9 BANK0 RO When 1, indicates that the DCM that deskews the ZBT SSRAM clock is locked.
15:10   RO/MBZ (Reserved)
ADM-XP
Bits Mnemonic Type Function
8 MEMCLK RO When 1, indicates that the DCM that generates the clock for the memory clock domain is locked.
15:9   RO/MBZ (Reserved)
ADM-XRC-4LX and ADM-XRC-4SX
Bits Mnemonic Type Function
8 MEMCLK RO When 1, indicates that the DCM that generates the clock for the memory clock domain is locked.
9 ZBT RO When 1, indicates that the DCM that deskews the clock for the ZBT SSRAMs is locked.
15:10   RO/MBZ (Reserved)
ADM-XRC-4FX and ADPE-XRC-4FX
Bits Mnemonic Type Function
8 MEMCLK RO When 1, indicates that the DCM that generates the clock for the memory clock domain is locked.
9 IDELAY RO When 1, indicates that the IDELAYCTRL instances are locked to the IDELAY reference clock.
15:10   RO/MBZ (Reserved)
ADM-XRC-5LX, ADM-XRC-5T1, ADM-XRC-5T2, ADM-XRC-5T2-ADV and ADM-XRC-5T-DA1
Bits Mnemonic Type Function
8 MEMCLK RO When 1, indicates that the PLL that generates the clocks for the memory clock domain is locked.
9 IDELAY RO When 1, indicates that the IDELAYCTRL instances are locked to the IDELAY reference clock.
15:10   RO/MBZ (Reserved)
ADM-XRC-5TZ
Bits Mnemonic Type Function
8 MEMCLK RO When 1, indicates that the DCM that buffers the clock for the memory clock domain is locked.
9 RAMCLK RO When 1, indicates that the DCM that deskews the clocks driven to the ZBT SSRAM devices is locked.
10 IDELAY RO When 1, indicates that the IDELAYCTRL instances are locked to the IDELAY reference clock.
15:11   RO/MBZ (Reserved)

Memory status register (MEMSTAT, local bus address 0x18)

This register indicates whether or not training of memory banks has been successful. The precise bit-field definitions depend upon the model in use.
Bits Mnemonic Type Function
ADM-XRC, ADM-XRC-P and ADM-XRC-4SX
3:0 ZBT RO This field always returns 0xf, because the ZBT SSRAM ports do not require training.
31:4   RO/MBZ (Reserved)
ADM-XRC-II-Lite
1:0 ZBT RO This field always returns 0x3, because the ZBT SSRAM ports do not require training.
31:2   RO/MBZ (Reserved)
ADM-XRC-II, ADM-XRC-4LX and ADM-XRC-5TZ
5:0 ZBT RO This field always returns 0x3F, because the ZBT SSRAM ports do not require training.
31:6   RO/MBZ (Reserved)
ADM-XPL
0 ZBT RO This field always returns 1, because the ZBT SSRAM port does not require training.
1 SDRAM RO This field returns 1 if the DDR SDRAM has completed training successfully, otherwise 0.
31:2   RO/MBZ (Reserved)
ADM-XP
3:0 SSRAM RO This field returns a 1 in a bit position if the corresponding DDR-II SSRAM port has completed training successfully, otherwise 0.
5:4 SDRAM RO This field returns a 1 in a bit position if the corresponding DDR SDRAM port has completed training successfully, otherwise 0.
31:6   RO/MBZ (Reserved)
ADM-XRC-4FX, ADPE-XRC-4FX and ADM-XRC-5LX
3:0 SDRAM RO This field returns a 1 in a bit position if the corresponding DDR-II SDRAM port has completed training successfully, otherwise 0.
31:4   RO/MBZ (Reserved)
ADM-XRC-5T1
1:0 SDRAM RO This field returns a 1 in a bit position if the corresponding DDR-II SDRAM port has completed training successfully, otherwise 0.
2 SSRAM RO This field returns 1 if the DDR-II SSRAM port has completed training successfully, otherwise 0.
31:3   RO/MBZ (Reserved)
ADM-XRC-5T2 and ADM-XRC-5T2-ADV
3:0 SDRAM RO This field returns a 1 in a bit position if the corresponding DDR-II SDRAM port has completed training successfully, otherwise 0.
5:4 SSRAM RO This field returns 1 in a bit position if the corresponding DDR-II SSRAM port has completed training successfully, otherwise 0.
31:6   RO/MBZ (Reserved)
ADM-XRC-5T-DA1
1:0 SDRAM RO This field returns a 1 in a bit position if the corresponding DDR-II SDRAM port has completed training successfully, otherwise 0.
3:2 SSRAM RO This field returns 1 if a bit position if the corresponding DDR-II SSRAM port has completed training successfully, otherwise 0.
31:4   RO/MBZ (Reserved)

Memory bank mode registers (MODE0...MODE15, local bus address 0x40...0x7C)

There are a total of 16 MODE registers, occupying local bus addresses 0x40 to 0x7C inclusive. The interpretation of the fields in a mode register depends upon the type of memory that the register corresponds to.
ZBT SSRAM
Bits Mnemonic Type Function
0 PIPELINE R/W When this field is 0, the memory port expects the ZBT SSRAM to be operating in flowthrough mode. When this field is 1, the memory port expects the ZBT SSRAM to be operating in pipelined mode.
31:1   MBZ (Reserved)
DDR-II SSRAM
Bits Mnemonic Type Function
0 BLEN R/W When this field is 0, the memory port expects the DDR-II SSRAM device to be a burst length 2 device. When this field is 1, the memory port expects the DDR-II SSRAM device to be a burst length 2 or 4 device.
1   MBZ (Reserved)
2 DLLOFF R/W When this field is 0, the memory port enables the DLL (delay locked loop) within the DDR-II SDRAM device (this is the normal mode of operation). When this field is 1, the memory port disables the DLL (not recommended).
31:3   MBZ (Reserved)
DDR SDRAM
Bits Mnemonic Type Function
0 REG R/W When this field is 0, the memory port expects the DDR SDRAM to be unregistered. When this field is 1, the memory port expects the DDR SDRAM to be registered.
1   MBZ Reserved for implementing X4 DDR SDRAM device support (must be zero in this release of the SDK).
3:2 ROWS R/W This field specifies the number of row address bits in the DDR SDRAM devices:
0x0 => 12 bits
0x1 => 13 bits
0x2 => 14 bits
0x3 => 15 bits
5:4 COLS R/W This field specifies the number of column address bits in the DDR SDRAM devices. The number of column address bits depends on this field and also the ROWS field, as follows:
0x0 => (#rows - 4)
0x1 => (#rows - 3)
0x2 => (#rows - 2)
0x3 => (#rows - 1)
For example, if ROWS = 0x1 and COLS = 0x1, then the number of column address bits is (13 - 3) = 10.
7:6 BANKS R/W This field selects the number of bank address bits in the DDR SDRAM devices:
0x0 => no bank bits, 1 internal bank
0x1 => 1 bank bit, 2 internal banks
0x2 => 2 bank bits, 4 internal banks
0x3 => 3 bank bits, 8 internal banks
9:8 PBANKS R/W This field selects the number of chip select pins in the memory bank:
0x0 => 1 physical bank
0x1 => 2 physical banks
0x2 => 4 physical banks
0x3 => 8 physical banks
31:10   MBZ  
DDR-II SDRAM
Bits Mnemonic Type Function
0   R/W This field is reserved for implementing registered DDR-II SDRAM support (must be zero in this release of the SDK).
1   MBZ This field is reserved for implementing X4 DDR-II SDRAM device support (must be zero in this release of the SDK).
3:2 ROWS R/W This field specifies the number of row address bits in the DDR-II SDRAM devices:
0x0 => 12 bits
0x1 => 13 bits
0x2 => 14 bits
0x3 => 15 bits
5:4 COLS R/W This field specifies the number of column address bits in the DDR-II SDRAM devices. The number of column address bits depends on this field and also the ROWS field, as follows:
0x0 => (#rows - 4)
0x1 => (#rows - 3)
0x2 => (#rows - 2)
0x3 => (#rows - 1)
For example, if ROWS = 0x1 and COLS = 0x1, then the number of column address bits is (13 - 3) = 10.
7:6 BANKS R/W This field selects the number of bank address bits in the DDR-II SDRAM devices:
0x0 => no bank bits, 1 internal bank
0x1 => 1 bank bit, 2 internal banks
0x2 => 2 bank bits, 4 internal banks
0x3 => 3 bank bits, 8 internal banks
9:8 PBANKS R/W This field selects the number of chip select pins in the memory bank:
0x0 => 1 physical bank
0x1 => 2 physical banks
0x2 => 4 physical banks
0x3 => 8 physical banks
31:10   MBZ  

USER registers (USER0...USER63, local bus address 0x100...0x1FF)

There are a total of 64 USER registers, occupying local bus addresses 0x100 to 0x1FF inclusive. The interpretation of the USER registers depends upon the logic within the user_app module, and the description below applies only to the unmodified user_app module that ships with this SDK.
USER0 - USER15

The first 16 user registers specify the starting addresses, counting in logical data words, where the chip-driven memory test should begin testing each memory bank.
Bits Mnemonic Type Function
31:0 OFFSET R/W Specifies the starting address at which to begin testing a particular memory bank.
USER16 - USER31

The next 16 user registers specify the number of logical data words that the chip-driven memory test should test in each bank.
Bits Mnemonic Type Function
31:0 LENGTH R/W Specifies the number of logical data words to test in a particular memory bank, minus 1. For example, to test 1 megaword, write the value 0xFFFFF.
USER48

The USER48 register indicates on which phase the memory test failed for banks 0 to 3.
Bits Mnemonic Type Function
7:0 EPHASE0 RO If ERROR[0] is 1, indicates on which phase the memory test for bank 0 failed.
15:8 EPHASE1 RO If ERROR[1] is 1, indicates on which phase the memory test for bank 1 failed.
23:16 EPHASE2 RO If ERROR[2] is 1, indicates on which phase the memory test for bank 2 failed.
31:24 EPHASE3 RO If ERROR[3] is 1, indicates on which phase the memory test for bank 3 failed.
USER49

The USER48 registers indicates on which phase the memory test failed for banks 4 to 7.
Bits Mnemonic Type Function
7:0 EPHASE4 RO If ERROR[4] is 1, indicates on which phase the memory test for bank 4 failed.
15:8 EPHASE5 RO If ERROR[5] is 1, indicates on which phase the memory test for bank 5 failed.
23:16 EPHASE6 RO If ERROR[6] is 1, indicates on which phase the memory test for bank 6 failed.
31:24 EPHASE7 RO If ERROR[7] is 1, indicates on which phase the memory test for bank 7 failed.
USER50

The USER50 register indicates on which phase the memory test failed for banks 8 to 11.
Bits Mnemonic Type Function
7:0 EPHASE8 RO If ERROR[8] is 1, indicates on which phase the memory test for bank 8 failed.
15:8 EPHASE9 RO If ERROR[9] is 1, indicates on which phase the memory test for bank 9 failed.
23:16 EPHASE10 RO If ERROR[10] is 1, indicates on which phase the memory test for bank 10 failed.
31:24 EPHASE11 RO If ERROR[11] is 1, indicates on which phase the memory test for bank 11 failed.
USER51

The USER50 register indicates on which phase the memory test failed for banks 12 to 15.
Bits Mnemonic Type Function
7:0 EPHASE12 RO If ERROR[12] is 1, indicates on which phase the memory test for bank 12 failed.
15:8 EPHASE13 RO If ERROR[13] is 1, indicates on which phase the memory test for bank 13 failed.
23:16 EPHASE14 RO If ERROR[14] is 1, indicates on which phase the memory test for bank 14 failed.
31:24 EPHASE15 RO If ERROR[11] is 1, indicates on which phase the memory test for bank 15 failed.
USER63

The USER63 register is used to initiate the chip-driven memory test, as well as check the status of the memory test. When one of the low 16 bits is written with 1, it initiates the memory test for the corresponding memory bank, using the parameters in the USER0 - USER31 registers. To initiate the memory test on several banks simultaneously, write a number of 1s to USER63[15:0] at the same time.
Bits Mnemonic Type Function
15:0 DONE (R)
GO (W)
R/W When read, returns 1 for a particular bit if the memory test for the corresponding bank is not running. Banks that are nonexistent or unused always return 1.
When written with 1, initiates the memory test for the corresponding memory bank. For example, writing 0xB would initiate the memory test for banks 0, 1 and 3 only. Writing a 1 to a bit that corresponds to a nonexistent or unused bank has no effect.
31:16 ERROR RO Returns a 1 for a particular bit if one or more errors occurred during the memory test for the corresponding memory bank. Valid only when the corresponding bit of the DONE field is 1. For each bit of ERROR indicates that failure, the corresponding EPHASE field may be inspected in order to discover the phase of the memory test in which the first failure occurred.

Explanation of design

At the highest level of abstraction, the design consists of 3 logical blocks:

High-level view of the MEMORY reference design.

The local bus interface enables the CPU to read and write the memory banks. At the same time, the "user application" module can also read and write the memory banks. The local bus interface and the user application also communicate with each other via a set of registers. The user application as supplied in this SDK is in fact a chip-driven memory test, which can test all memory banks simultaneously on command from the host. The user can rewrite the user application, replacing the memory test logic with whatever processing logic he or she requires.

Because the FPGA space is limited to 4MB on most models, the local bus interface of the design divides the FPGA space into a lower 2MB region for registers and an upper 2MB window for accessing the memory. A bank register selects which bank is currently being accessed, and a page register is provided so that all of a large memory bank can be accessed even though the window through which it is accessed is 2MB in size. The "user application", on the other hand, has no such restrictions. It can access all banks of memory simultaneously without need for page or bank selection.

Explanation of memory_main module

The following is a block diagram of the memory_main module, which is not specific to any model and has been written in such a way that it expects to be wrapped up by a model-specific wrapper. It implements the local bus interface and the FPGA registers. It also contains the one and only instance of the memory_banks module as well as the one and only instance of the user_app module.

The memory_main module.

As a brief aside, the wrapper for the module memory_main is model-specific, and is also the top-level of the design. For example, there is an an ADM-XPL-specific wrapper module in the source file xpl/memory-xpl.vhd that instantiates the one and only instance of the memory_main module and takes care of some ADM-XPL-specific details, such as inputting global clocks.

Explanation of memory_banks module

As mentioned above, the memory_main module encloses one instance of the memory_banks module. The memory_banks module is entirely model-specific and comes in several versions, one per model. Its job is fourfold:

  1. To present a uniform interface in the local bus clock domain to the memory_main module no matter what type of memory devices are present for a given model.
  2. To decouple the local bus clock domain from the memory clock domain, as the two clock domains are generally independent in phase and frequency.
  3. To instantiate memory ports that are appropriate to the model. For example, the ADM-XRC-4FX version of the memory_banks module instantiates four DDR-II SDRAM ports.
  4. To handle any difference in the width of the local bus data (32 bits) and the width of the logical data written to and read from the memory ports:
  5. To share the memory ports between the local bus interface and the user application by instantiating one arbitration module (arbiter_2) per memory port.

The following figure illustrates the data flow within xrc4fx/memory_banks-xrc4fx.vhd. This is the ADM-XRC-4FX specific version of the memory_banks module:

Data flow within the memory_banks module.

When data is written to a memory bank, the port_repl module takes 32-bit data words from the local bus interface on mem_d and and assembles them into words suitable for the memory ports (in this case, DDR-II SDRAM ports whose logical data with is 128). A set of async_port instances bridge the local bus clock domain and the memory clock domain. In the memory clock domain, a set of arbiter_2 instances connect together both the preceding async_port instances and the user application to the memory ports (ddr2sdram_port instances).

When data is read from a memory bank, logical data words flow from the memory ports, through the arbiter_2 instances, and through the async_port instances. A multiplexor selects the data from a particular async_port according to the current value of the BANK register. Finally, the port_mux instance performs width conversion from logical data words (128 bits) to the local bus data width (32 bits), outputting the data on mem_q.

Explanation of memory_banks module - inbound datapath

Continuing with the ADM-XRC-4FX version as an example, the following figure shows detail for the data path from the local bus interface to the memory banks:

Detail of inbound datapath in the memory_banks module.

The currently selected bank is available as a one-hot vector sel_bank_1h. This is used to ensure that at most one set of port_p* signals can be active at a given moment, in turn ensuring that at most one async_port instance can be active at any time. The port_p* signals are generated in a fairly trivial manner from the mem_* signals, which work as follows:

Explanation of memory_banks module - outbound datapath

Detail of outbound datapath in the memory_banks module.

As in the inbound datapath, the one-hot bank-select vector sel_bank_1h is used to ensure that at most one set of port_p* signals can be active at a given moment, in turn ensuring that at most one async_port instance can be active at any time. When the local bus interface reads a memory bank, the mem_* signals work as follows:

Explanation of memory_banks module - memory arbitration

The final figure in this discussion shows how each memory port is shared between the local bus interface (represented by an async_port and the user_app module, with reference to the ADM-XRC-4FX:

Detail of logic for sharing a memory bank within the memory_banks module.

In the above figure, only the logic for a single memory bank is shown, but each memory bank has an identical set of logic consisting of an async_port, an arbiter_2 and a ddr2sdram_port. There are a number of generic signals that work in the same way regardless of the type of memory to which the memory port interfaces. These signals work as follows:

In addition to the generic memory port signals, a particular type of memory port may have one or more sideband signals that are specific to that particular type of memory port. In the above figure, the ddr2sdram_port module has four sideband signals that specify the paramters of the memory devices that it is controlling. They are: row, col, bank and pbank, and their values are determined by the bit fields in the MODE register that is described above, for the case of a DDR-II SDRAM memory bank.

Explanation of user_app module

The user_app module is intended to be a starting point for the end-user to add his or her own logic to perform some useful data processing function. As shipped in this SDK, it contains logic to perform a chip-driven memory test of all banks of on-board memory. See the MemoryF example application for details on how to run the chip-driven memory test.

Implementation of chip-driven memory test in user_app module.

The end-user can remove, modify and add logic as desired in order to create a customized user_app module. In doing so, a few points to remember are:

A facility for the local bus interface to communicate with the user_app module and vice-versa is provided by the three signals reg_in, reg_wr and reg_out. Within the local bus address space, there is provision for 64 32-bit registers, totalling 256 bytes of registers. When the CPU writes to a USER register in the range local bus addresses 0x100 to 0x1FF, the write is reflected in the values of reg_in and reg_wr. For example, if the CPU writes a 16-bit value to the address 0x13e, the 16-bit value is reflected in reg_in[31:16], while bits 62 and 63 (only) of reg_wr pulse asserted for exactly one memory / user clock cycle. When such an event occurs, the user_app module can, at its discretion, elect to store the value on reg_in somewhere.

The user_app module can drive the reg_out vector, which is 256 bytes in size, with arbitrary status information. This status information is visible in the USER registers when the CPU reads local bus addresses 0x100 to 0x1FF.

Note that synchronizing logic in the reg_sync module results in a round-trip delay of approximately 12 local bus clock cycles whenever some information must be communicated between the local bus interface and the user_app module. Hence, if the CPU writes something to a USER register, reading the same or another USER register is not guaranteed to return a value that reflects what was just written until approximately 12 local bus clock cycles have elapsed.

Source files

For a list of the VHDL source files, refer to the appropriate XST project file, as referenced in the following table:

Model XST script file XST project file UCF file
ADM-XRC with Virtex memory-xrc-v.scr memory-xrc-v.prj xrc/memory-xrc-v.ucf
ADM-XRC with Virtex-E/-EM memory-xrc-ve.scr memory-xrc-ve.prj xrc/memory-xrc-ve.ucf
ADM-XRC-P with Virtex memory-xrcp-v.scr memory-xrcp-v.prj xrcp/memory-xrcp-v.ucf
ADM-XRC-P with Virtex-E/-EM memory-xrcp-ve.scr memory-xrcp-ve.prj xrcp/memory-xrcp-ve.ucf
ADM-XRC-II-Lite memory-xrc2l-v2.scr memory-xrc2l-v2.prj xrc2l/memory-xrc2l.ucf
ADM-XRC-II memory-xrc2-v2.scr memory-xrc2-v2.prj xrc2/memory-xrc2.ucf
ADM-XPL with 2VP7 memory-xpl-v2p.scr memory-xpl-v2p.prj xpl/memory-xpl-2vp7.ucf
ADM-XPL with 2VP20 or 2VP30 memory-xpl-v2p.scr memory-xpl-v2p.prj xpl/memory-xpl-2vp20.ucf
ADM-XP with 2VP70 memory-xp-v2p.scr memory-xp-v2p.prj xp/memory-xp-2vp70.ucf
ADM-XP with 2VP100 memory-xp-v2p.scr memory-xp-v2p.prj xp/memory-xp-2vp100.ucf
ADM-XRC-4LX memory-xrc4lx-v4lx.scr memory-xrc4lx-v4lx.prj xrc4lx/memory-xrc4lx.ucf
ADM-XRC-4SX memory-xrc4sx-v4sx.scr memory-xrc4sx-v4sx.prj xrc4sx/memory-xrc4sx.ucf
ADM-XRC-4FX with 4VFX100 memory-xrc4fx-v4fx.scr memory-xrc4fx-v4fx.prj xrc4fx/memory-xrc4fx-4vfx100.ucf
ADM-XRC-4FX with 4VFX140 memory-xrc4fx-v4fx.scr memory-xrc4fx-v4fx.prj xrc4fx/memory-xrc4fx-4vfx140.ucf
ADPE-XRC-4FX with 4VFX100 memory-xrce4fx-v4fx.scr memory-xrce4fx-v4fx.prj xrce4fx/memory-xrce4fx-4vfx100.ucf
ADPE-XRC-4FX with 4VFX140 memory-xrce4fx-v4fx.scr memory-xrce4fx-v4fx.prj xrce4fx/memory-xrce4fx-4vfx140.ucf
ADM-XRC-5LX memory-xrc5lx-v5lx.scr memory-xrc5lx-v5lx.prj xrc5lx/memory-xrc5lx.ucf
ADM-XRC-5T1 with V5FXT memory-xrc5t1-v5fxt.scr memory-xrc5t1-v5fxt.prj xrc5t1/memory-xrc5t1-5vfxt.ucf
ADM-XRC-5T1 with V5LXT memory-xrc5t1-v5lxt.scr memory-xrc5t1-v5lxt.prj xrc5t1/memory-xrc5t1.ucf
ADM-XRC-5T1 with V5SXT memory-xrc5t1-v5sxt.scr memory-xrc5t1-v5sxt.prj xrc5t1/memory-xrc5t1.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with V5LX110T, V5LX155T or V5LX220T memory-xrc5t2-v5lxt_4banks.scr memory-xrc5t2-v5lxt_4banks.prj xrc5t2/memory-xrc5t2-5vlx110t.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with V5LX330T memory-xrc5t2-v5lxt_6banks.scr memory-xrc5t2-v5lxt_6banks.prj xrc5t2/memory-xrc5t2-5vlx330t.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with V5FX100T memory-xrc5t2-v5fxt_4banks.scr memory-xrc5t2-v5fxt_4banks.prj xrc5t2/memory-xrc5t2-5vfx100t.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with V5FX130T memory-xrc5t2-v5fxt_4banks.scr memory-xrc5t2-v5fxt_4banks.prj xrc5t2/memory-xrc5t2-5vfx130t.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with V5FX200T memory-xrc5t2-v5fxt_6banks.scr memory-xrc5t2-v5fxt_6banks.prj xrc5t2/memory-xrc5t2-5vfx200t.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with V5SX240T memory-xrc5t2-v5sxt_6banks.scr memory-xrc5t2-v5sxt_6banks.prj xrc5t2/memory-xrc5t2-5vsx240t.ucf
ADM-XRC-5TZ with V5LX110T, V5LX155T or V5LX220T memory-xrc5tz-v5lxt.scr memory-xrc5tz-v5lxt.prj xrc5t2/memory-xrc5tz-5vlx110t.ucf
ADM-XRC-5TZ with V5LX330T memory-xrc5tz-v5lxt.scr memory-xrc5tz-v5lxt.prj xrc5t2/memory-xrc5tz-5vlx330t.ucf
ADM-XRC-5TZ with V5FX100T memory-xrc5tz-v5fxt.scr memory-xrc5tz-v5fxt.prj xrc5t2/memory-xrc5tz-5vfx100t.ucf
ADM-XRC-5TZ with V5FX130T memory-xrc5tz-v5fxt.scr memory-xrc5tz-v5fxt.prj xrc5t2/memory-xrc5tz-5vfx130t.ucf
ADM-XRC-5TZ with V5FX200T memory-xrc5tz-v5fxt.scr memory-xrc5tz-v5fxt.prj xrc5t2/memory-xrc5tz-5vfx200t.ucf
ADM-XRC-5TZ with V5SX240T memory-xrc5tz-v5sxt.scr memory-xrc5tz-v5sxt.prj xrc5t2/memory-xrc5tz-5vsx240t.ucf
ADM-XRC-5T-DA1 with V5FXT memory-xrc5tda1-v5fxt.scr memory-xrc5tda1-v5fxt.prj xrc5tda1/memory-xrc5tda1-5vfxt.ucf
ADM-XRC-5T-DA1 with V5LXT memory-xrc5tda1-v5lxt.scr memory-xrc5tda1-v5lxt.prj xrc5tda1/memory-xrc5tda1.ucf
ADM-XRC-5T-DA1 with V5SXT memory-xrc5tda1-v5sxt.scr memory-xrc5tda1-v5sxt.prj xrc5tda1/memory-xrc5tda1.ucf

Project Navigator files

Project Navigator projects can be found in the projnav directory as follows:

Model Project Navigator project file
ADM-XRC projnav/xrc/<device>
ADM-XRC-P projnav/xrcp/<device>
ADM-XRC-II-Lite projnav/xrc2l/<device>
ADM-XRC-II projnav/xrc2/<device>
ADM-XPL projnav/xpl/<device>
ADM-XP projnav/xp/<device>
ADM-XRC-4LX projnav/xrc4lx/<device>
ADM-XRC-4SX projnav/xrc4sx/<device>
ADM-XRC-4FX projnav/xrc4fx/<device>
ADPE-XRC-4FX projnav/xrce4fx/<device>
ADM-XRC-5LX projnav/xrc5lx/<device>
ADM-XRC-5T1 projnav/xrc5t1/<device>
ADM-XRC-5T2
ADM-XRC-5T2-ADV
projnav/xrc5t2/<device>
ADM-XRC-5TZ projnav/xrc5tz/<device>
ADM-XRC-5T-DA1 projnav/xrc5tda1/<device>

Modelsim scripts

Example Modelsim-compatible script files for simulating this design are provided. First change directory to where this design is located, and then refer to the following table for the appropriate shell commands for a particular model.

These simulations make use of behavioural memory models supplied by Micron and Hynix. These models are available from the websites of the respective vendors, but for legal reasons, Alpha Data does not supply these models with this SDK. The models in question are:

Note that simulations targetting models that use DDR-II SDRAM memory may require as much as 200 microseconds of simulated time for DLL/DCM/PLL locking and memory bank training to complete. This may result in long periods of inactivity on the local bus. Such periods of inactivity do not necesary indicate that the simulation is not working as expected. Some warnings may be emitted by memory models, DCMs, DLLs and PLLs. These relate to startup and can safely be ignored, as the design is held in reset until clocks have stabilized.

Model Shell command
ADM-XRC cd xrc
vsim -do "do memory-xrc.do"
ADM-XRC-P cd xrcp
vsim -do "do memory-xrcp.do"
ADM-XRC-II-Lite cd xrc2l
vsim -do "do memory-xrc2l.do"
ADM-XRC-II cd xrc2
vsim -do "do memory-xrc2.do"
ADM-XPL cd xpl
vsim -do "do memory-xpl.do"
ADM-XP cd xp
vsim -do "do memory-xp.do"
ADM-XRC-4LX cd xrc4lx
vsim -do "do memory-xrc4lx.do"
ADM-XRC-4SX cd xrc4sx
vsim -do "do memory-xrc4sx.do"
ADM-XRC-4FX cd xrc4fx
vsim -do "do memory-xrc4fx.do"
ADPE-XRC-4FX cd xrce4fx
vsim -do "do memory-xrce4fx.do"
ADM-XRC-5LX cd xrc5lx
vsim -do "do memory-xrc5lx.do"
ADM-XRC-5T1 cd xrc5t1
vsim -do "do memory-xrc5t1.do"
ADM-XRC-5T2
ADM-XRC-5T2-ADV
cd xrc5t2
vsim -do "do memory-xrc5t2.do"
ADM-XRC-5TZ cd xrc5tz
vsim -do "do memory-xrc5tz.do"
ADM-XRC-5T-DA1 cd xrc5tda1
vsim -do "do memory-xrc5tda1.do"

 


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