ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data
Model | Supported |
ADM-XRC | ![]() |
ADM-XRC-P | ![]() |
ADM-XRC-II-Lite | ![]() |
ADM-XRC-II | ![]() |
ADM-XPL | ![]() |
ADM-XP | ![]() |
ADP-WRC-II | ![]() |
ADP-DRC-II | ![]() |
ADP-XPI | ![]() |
ADM-XRC-4LX | ![]() |
ADM-XRC-4SX | ![]() |
ADM-XRC-4FX | ![]() |
ADPE-XRC-4FX | ![]() |
ADM-XRC-5LX | ![]() |
ADM-XRC-5T1 | ![]() |
ADM-XRC-5T2 | ![]() |
ADM-XRC-5T2-ADV | ![]() |
ADM-XRC-5TZ | ![]() |
ADM-XRC-5T-DA1 | ![]() |
The Simple sample application demonstrates how to implement registers in the FPGA that are accessible from the host using direct slave cycles.
simple [options ...]
Option | Type | Meaning |
-card | base 10 integer | ID of card to open |
-index | base 10 integer | Index of card to open |
-64 | Operate local bus in 32 bit mode (default) | |
+64 | Operate local bus in 64 bit mode |
The user enters hexadecimal values, which the application writes to a register in the FPGA. The application reads the values back from the FPGA and displays them. However, the FPGA nibble-reverses the values before returning them.
Normally, this application uses the Simple sample FPGA design (Verilog, VHDL). However, if the +64 option is specified on the command line, the Simple64 sample FPGA design (Verilog, VHDL) is used instead. It is important to note that when the 64-bit version is used, the application does nothing different apart from configuring the FPGA local bus space to operate in 64-bit mode (see ADMXRC2_SetSpaceConfig).