ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data
The ddrsdram_training_v2 component is part of the memif package and implements the training algorithm for one or more instances of the ddrsdram_port_v2 component.
This module works by sweeping the phase of a capture clock clkc0, which clocks data from the memory devices into the FPGA's IOBs, from -180 degrees to +180 degrees. During the sweep, the associated memory ports that are being trained are instructed to perform readback experiments in order to find a window where data can be reliably captured from the memory devices. A number of sweeps are performed because, as well as varying the phase, the amount of coarse-grained delay must also be varied in order to determine the delay between issuing a command to the memory devices and valid data being captured. The training algorithm can be expressed in pseudocode as:
trained := 0 tstcomp := 0 best_cedge := invalid best_window := 0 best_phase := invalid for cedge in 0 to 7 loop window_start := invalid window_stop := invalid in_window := false for phase in -180 to +180 do set phase of clkc0 to 'phase' instruct memory ports to perform readback experiment via 'tstdo' signal if 'tstdone' and 'tstok' indicate experiment was successful for all memory ports then if not in_window then // Start of window detected window_start := phase in_window := true end if else if in_window then // End of window detected window_stop := phase window_length := window_stop - window_start if window_length > some_minimum_window and window_length > best_window // This is the new best window best_window := window_length best_cedge := cedge best_phase := (window_stop + window_start) / 2 end if in_window := false end if end if end if if in_window then // Handle special case where we're still inside window at end of phase sweep window_stop := +180 window_length := window_stop - window_start if window_length > some_minimum_window and window_length > best_window // This is the new best window best_window := window_length best_cedge := cedge best_phase := (window_stop + window_start) / 2 end if end if end loop // Training completed tstcomp := 1 if best_window > 0 then trained := 1 // Training completed and successful, so set operating parameters set phase of clkc0 to 'best_phase' cedge := best_cedge end if
Projects making use of this component must include all of the following source files (relative to root of SDK installation):
fpga/vhdl/common/memif/memif_pkg.vhd
fpga/vhdl/common/memif/memif_int_pkg.vhd
fpga/vhdl/common/memif/memif_def_synth.vhd OR fpga/vhdl/common/memif/memif_def_sim.vhd
fpga/vhdl/common/memif/ddrsdram_v2/ddrsdram_training_v2.vhd
If synthesizing, the file fpga/vhdl/common/memif/memif_def_synth.vhd must be included. If simulating, the file fpga/vhdl/common/memif/memif_def_sim.vhd must be included instead.
Name | Type | Function | Note |
num_port | natural | This is the width in bits of the tstdone and tstok ports. | 1 |
Notes:
The signals of this interface to and from the user application are as follows:
Signal | Type | Function | Note |
cedge | in | Capture edge This should be connected directly to the cedge ports of one or more instances of ddrsdram_port_v2, and carries information about how to retime data captured using the clkc0 and clkc180 clocks into the memory ports' user interface clock domain. |
|
clk | in | Clock All ports except rst, clkc, clkc0 and clkc180 are synchronous to clk. |
2, 3 |
clkc | in | Capture clock in This clock is used to generate the two capture clock phases clkc0 and clkc180. |
4 |
clkc0 | out | Capture clock phase 0 This clock should be connected directly to the clkc0 ports of one or more instances of ddrsdram_port_v2, and is used to clock data read from the DDR SDRAM devices into the FPGA's IOBs. |
4 |
clkc180 | out | Capture clock phase 180 This clock is the same frequency as clkc0 but 180 degrees out of phase, and should be connected directly to the clkc180 ports of one or more instances of ddrsdram_port_v2. It is used to clock data read from the DDR SDRAM devices into the FPGA's IOBs. |
4 |
rst | in | Asychronous reset Asserting this signal returns the module to its default state, so that it will begin the training sequence when rst is deasserted. This port may be tied to logic 0 if not required. |
|
sr | in | Sychronous reset Asserting this signal returns the module to its default state, so that it will begin the training sequence when sr is deasserted. This port may be tied to logic 0 if not required. |
|
tstcomp | out | Training complete to memory port This signal should be connected directly to the tstcomp ports of one or more instances of ddrsdram_port_v2, and notifies those ports that training is complete and normal operation should begin. |
|
tstdo | out | Do readback experiment This signal should be connected directly to the tstdo ports of one or more instances of ddrsdram_port_v2, and instructs those ports to perform a readback experiment (as part of the training sequence). |
|
tstdone | in | Done readback experiment This signal is a vector where each bit of the vector should be connected directly to the tstdone port of an instance of ddrsdram_port_v2. The ddrsdram_port_v2 instance pulses this signal when it has completed a readback experiment (as part of the training sequence). |
|
tstok | in | Readback experiment successful This signal is a vector where each bit of the vector should be connected directly to the tstok port of an instance of ddrsdram_port_v2. The ddrsdram_port_v2 instance asserts this signal, qualified by the corresponding bit of the tstdone vector, when a readback experiment is completed without error. |
|
trained | out | Training successful This signal is asserted when training has been completed for all associated ddrsdram_port_v2 instances and was successful (i.e. a data capture window was found for all memory ports). If training is completed but was unsuccessful (i.e. a data capture window could not be found for one or more of the memory ports), this signal will remain deasserted even though training has been completed. |
Notes:
Using this component to train one or more ddrsdram_port_v2 instances takes no more than 1.5 milliseconds assuming a clk frequency of 133 MHz. This time is measured from deassertion of rst or sr to assertion of trained. The number of memory ports does not affect the time required to train them.