ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


PLXSIM VHDL reference - locbus_agent_mux32

Declaration

Synopsis

Description

Declaration
component locbus_agent_mux32
    generic(
        tco_bussed : in    time := 5 ns;
        tco_p2p    : in    time := 5 ns);
    port(
        lreset_l   : in    std_logic;
        lclk       : in    std_logic;
        lad        : inout std_logic_vector(31 downto 0);
        lads_l     : inout std_logic;
        lbe_l      : inout std_logic_vector(3 downto 0);
        lblast_l   : inout std_logic;
        lbterm_l   : inout std_logic;
        lready_l   : inout std_logic;
        lwrite     : inout std_logic;
        lhold      : out   std_logic;
        lholda     : in    std_logic;
        bus_in     : out   locbus_in_t;
        bus_out    : in    locbus_out_t);
end component;
Synopsis

Non-synthesizable testbench component that drives the local bus.

Description

This local bus agent component can be instantiated in a testbench to drive a local bus that has a 32-bit multiplexed address/data bus. Each local bus agent is normally associated with a stimulus process. In the figure above, the signals on the right comprise the local bus, while the signals on the left are driven by the stimulus process.

The generics should be mapped as follows:

Generic Map to...
tco_bussed A value of type time that represents the desired local bus clock-to-output delay for the bussed signals (such as LADS#). This parameter has a suitable default value so it need not be specified.
tco_p2p A value of type time that represents the desired local bus clock-to-output delay for point to point signals (such as LHOLD). This parameter has a suitable default value so it need not be specified.

The first group of ports must be mapped to signals driven or used by the stimulus process associated with the local bus agent:

Port Map to...
bus_in A signal of type locbus_in_t, used by the stimulus process.
bus_out A signal of type locbus_out_t, driven by the stimulus process.

The second group of ports must be mapped to signals driven or input by the local bus arbiter:

Port Map to...
lhold A signal corresponding to LHOLD that is input by the bus arbiter. There should be one such signal per local bus agent.
lholda A signal corresponding to LHOLDA that is driven by the bus arbiter. There should be one such signal per local bus agent.

The remaining ports should be mapped to local bus signals as follows:

Port Map to...
lads_l The signal corresponding to LADS# in the testbench
lad The signal corresponding to LAD[31:0] in the testbench
lbe_l The signal corresponding to LBE#[3:0] in the testbench.
lclk The signal corresponding to LCLK in the testbench
lblast_l The signal corresponding to LBLAST# in the testbench.
lbterm_l The signal corresponding to LBTERM# in the testbench.
lready_l The signal corresponding to LREADY# in the testbench.
lreset_l The signal corresponding to LRESET# in the testbench
lwrite The signal corresponding to LWRITE in the testbench.

 


 Top of page