ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


Local bus signals

The table below lists the signals that comprise the local bus. There are some variations, between models in the ADM-XRC range, in the naming and number of signals. Refer to the notes for each signal for details.

Note Signal Driven by Description
  HOLD a local bus agent Hold

HOLD is asserted by a local bus agent in order to arbitrate for ownership of the local bus. It is not a bussed signal; each local bus agent that is capable of becoming a bus master has its own HOLD signal, which is an input to the local bus arbiter. When the arbiter grants ownership of the local bus, it asserts HOLDA.

An agent should not assert HOLD unless it intends to perform a burst as a master, and once it asserts HOLD, it should not deassert it until it has finished with the bus (for example, by completing a burst).

On an ADM-XRC series card, there are two local bus agents capable of performing local bus bursts as masters:
  • The HOLD signal for the local bus bridge is named LHOLD.
  • The HOLD signal for the FPGA is named FHOLD.
  HOLDA bus arbiter Hold Acknowledge

HOLDA is asserted by the bus arbiter to indicate that the bus has been granted to a particular local bus agent. It is not a bussed signal; each local bus agent that is capable of becoming a bus master has its own HOLDA signal, which is driven by the local bus arbiter.

The arbiter will not deassert a master's HOLDA until that master indicates that it has finished with the bus by deasserting its HOLD signal. An agent must not attempt to perform a local bus cycle as a master unless it has sampled its own HOLDA signal asserted.

On an ADM-XRC series card, there are two local bus agents capable of performing local bus bursts as masters:
  • The HOLDA signal for the local bus bridge is named LHOLDA.
  • The HOLDA signal for the FPGA is named FHOLDA.
  LADS# master Local Address Strobe

LADS# is asserted for exactly one cycle to mark the beginning of a burst. When LADS# is asserted, the local bus address is guaranteed to be valid on LA (for a nonmultiplexed address bus) or LAD (for a multiplexed address/data bus).
1 LA master Local Address

LA carries the local bus address of the current word of the current burst. It is valid for all cycles of a burst. When a word of data is transferred, the master normally increments LA, although a master may choose not to increment.

LA is present only on cards that have a nonmultiplexed address bus.
1 LAD master, slave Local Address/Data

LAD is qualified by the following events:
  • Assertion of LADS# by the master; LAD[31:0] carries the byte address of first word of burst. If the L64# signal exists on the bus and is asserted, then LAD[2:0] will be zero. Otherwise, LAD[1:0] will be zero.
  • Assertion of LBTERM# by the slave.
  • Assertion of LREADY# by the slave.
If the current transfer is 32 bits wide (L64# does not exist on the bus or is deasserted), then only LAD[31:0] carry data. If the current transfer is 64 bits wide (L64# exists on the bus and is asserted), then LAD[63:0] carry data.

LAD is present only on cards that have a multiplexed address/data bus.
  LBE# master Local Byte Enables

LBE# accompanies the LD or LAD signal, indicating which bytes of the data are valid. Together with the local bus address from LA or LAD, LBE# permits addressing of individual bytes.

LBE# is qualified by the following events:
  • Assertion of LBTERM# by the slave.
  • Assertion of LREADY# by the slave.
If the current transfer is 32 bits wide (L64# does not exist on the bus or is deasserted), then only LBE#[3:0] carry data. If the current transfer is 64 bits wide (L64# exists on the bus and is asserted), then LBE#[7:0] carry data.
  LBLAST# master Local Burst Last

LBLAST# is asserted by the master to indicate that the current word is the final word of the burst. When LREADY# is asserted along with LBLAST#, the current burst ends. LBLAST# is valid for every cycle of a burst.
2 LBTERM# slave Local Burst Terminate

LBTERM# is asserted by the slave to terminate the current burst immediately. The word of data on the LD or LAD bus is transferred, and the current burst ends, regardless of LREADY# and LBLAST#.
  LCLK central resources Local Bus Clock

LCLK is the local bus clock. All other local bus signals, with the exception of LRESET#, are synchronous to LCLK.

The frequency of LCLK is normally under the control of an application running on the host.
1 LD master, slave Local Data

LD is qualified by the following events:
  • Assertion of LBTERM# by the slave.
  • Assertion of LREADY# by the slave.
LD is present only on cards that have a nonmultiplexed address bus.
3 LREADY# slave Local Ready

LREADY# is asserted by the slave to indicate that the word of data currently on the LD or LAD bus has been transferred. If LBLAST# is also asserted, the current burst ends.
4 LRESET# local bus bridge Local Bus Reset

LRESET# is asserted asynchronously by the local bus bridge in order to cause all agents on the local bus to return to a known state, where they are not driving the local bus.
  LWRITE master Local Write

LWRITE indicates whether the current burst is a read or a write. If it is asserted, then the cycle is a write (the master drives data onto LD or LAD). LWRITE is valid for every cycle of a burst.
5 L64# master Local bus 64 bits

L64# indicates whether the current burst is a 32 bits or 64 bits wide. If it is asserted, then the cycle is a 64-bit burst where the master drives data onto LD[63:0] or LAD[63:0]). If it is deasserted, then the cycle is 32-bit burst where the master drives data onto LD[31:0] or LAD[31:0]. L64# is valid for every cycle of a burst.

This signal is not present in all models of the ADM-XRC range.

Note 1 - LA, LD & LAD

The ADM-XPL, ADM-XP, ADP-XPI, ADM-XRC-4FX, ADM-XRC-5LX and ADM-XRC-5T1 do not have the LA or LD busses. Instead, they have the LAD bus, which carries multiplexed address and data.

Note 2 - LBTERM# & LBTERMO#

Models featuring a PCI9080 as the local bus bridge (ADM-XRC, ADM-XRC-P, ADM-XRC-II-Lite) do not have a bussed LBTERM# signal. Instead, there is a pair of signals LBTERM# and LBTERMO# whose usage is as follows:

This pair of signals therefore performs the same function as a bussed LBTERM# signal, given that one of them is always unused in any particular cycle. In all other models, this arrangement has been rationalized into a single LBTERM# signal that can be driven by either the local bus bridge or the FPGA, depending on which is the master.

Note 3 - LREADY#, LREADYI# & LREADYO#

Models featuring a PCI9080 as the local bus bridge (ADM-XRC, ADM-XRC-P, ADM-XRC-II-Lite) do not have a bussed LREADY# signal. Instead, there is a pair of signals LREADYI# and LREADYO# whose usage is as follows:

This pair of signals therefore performs the same function as a bussed LREADY# signal, given that one of them is always unused in any particular cycle. In all other models, this arrangement has been rationalized into a single LREADY# signal that can be driven by either the local bus bridge or the FPGA, depending on which is the master.

Note 4 - LRESET#

In models featuring a PCI9080 (ADM-XRC, ADM-XRC-P, ADM-XRC-II-Lite), this signal is connected to the LRESETO# pin of the PCI9080. In all other, this signal is connected to the LRESET# pin of the PCI9656.

Note 5 - L64#

Only the following models are capable of 64-bit local bus operation and have the L64# signal: ADM-XPL, ADM-XP, ADP-XPI, ADM-XRC-4FX, ADM-XRC-5LX and ADM-XRC-5T1 .

 


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