ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


Direct slave transfers

Direct slave transfers are the basic method of transferring data to and from the FPGA on an ADM-XRC series card. The local bus bridge is the master, and the FPGA is the slave. Direct slave transfers are normally the result of calling functions from the API such as ADMXRC2_Read and ADMXRC2_DoDMA.

This section contains timing diagrams that illustrate the local bus protocol:

Single word read and write

Burst read, normal termination

Burst write, normal termination

Burst read, terminated by LBTERM#

Burst write, terminated by LBTERM#

Multiplexed address/data bus

Single word read and write

The following timing diagram illustrates a single word read followed by a single word write followed by another single word read, all terminated normally (LBLAST# and LREADY# are both asserted).

Note:

  1. The red lines indicate signals that the master may drive.
  2. The blue lines indicate signals that the currently addressed slave may drive. A slave must not drive these signals unless it has been addressed in the cycle when LADS# was asserted.
  3. It is recommended that the slave actively drive LREADY# and LBTERM# high for one cycle at the end of a burst, because resistive pullups on these lines may not cause them to transition high in time for the next burst (which may address a different slave). Cycles where this should be done are indicated by the symbols.
  4. It is recommended that a slave keeps its LREADY# and LBTERM# pins tristated in the cycle following LADS#, to avoid the possibility of contention with a previous slave that is slow to tristate its LREADY# and LBTERM# pins.
  5. Some models may assert LBLAST# in the same cycle as LADS# when a single word transfer is being performed. Applications should avoid being sensitive to this behavior.
  6. With a nonmultiplexed address bus, the same master may a new cycle (marked by the assertion of LADS#) immediately after the current cycle terminates. Compare with multiplexed address/data bus.

Burst read, normal termination

The following diagram illustrates a burst read, terminated normally (LBLAST# and LREADY# are both asserted).

Burst write, normal termination

The following diagram illustrates a burst write, terminated normally (LBLAST# and LREADY# are both asserted).

Burst read, terminated by LBTERM#

The following diagram illustrates a burst read, terminated by LBTERM#.

Note:

  1. LBTERM# overrides LREADY# and LBLAST#.

Burst write, terminated by LBTERM#

The following diagram illustrates a burst write, terminated by LBTERM#.

Note:

  1. LBTERM# overrides LREADY# and LBLAST#.

Multiplexed address/data bus

The following diagram illustrates the difference in the local bus protocol on models with a multiplexed address/data bus.

Note:

  1. LAD replaces LA and LD. The slave must internally track the local bus address as each word of data is transferred.
  2. When a master performs a burst read, the slave must not drive LAD in the cycle following the assertion of LADS# and must not assert LBTERM# or LREADY# in that cycle.
  3. In order to allow LAD to turn around, a master must not attempt to begin a new burst (by asserting LADS# and driving LAD) in the cycle following the final cycle of a read. For simplicity, a master may elect to also apply this rule to writes.

 


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