ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


PLXDSSM - A practical example

PLXDSSM module definition

PLXDSSM state diagram

PLXDSSM timing diagrams

This section describes the PLXDSSM state machine that is used in most of the sample FPGA designs. It is used as a building block in the implementation of a local bus interface that responds to Direct Slave transfers.

PLXDSSM module definition

PLXDSSM can be visualized as the following module:

The upper section of the module shows general signals such as clock, asynchronous reset and synchronous reset (either or both types of reset may be used). Below those, on the left hand section of the module, are the local bus signals, possibly qualified in some manner which is discussed below. The signals on the right hand are signals to and from the application logic. The functions of the signals are as follows:

Signal Direction Description
clk IN This signal is the local bus clock.
rst IN Asynchronous reset; if used, should be derived from the local bus reset signal LRESET#.
sr IN Synchronous reset; if used, should be derived from the local bus reset signal LRESET#.
qlads IN This signal must be a suitably qualified active-high version of the local bus address strobe LADS#. Typically obtained from a combinatorial function such as

qlads <= !LADS# and !LA[23] and !FHOLDA
lblast IN This signal should simply be an active-high version of the local bus LBLAST# signal.
lwrite IN This signal should simply be the local bus LWRITE signal.
lready_o_l OUT This signal should normally be driven onto the local bus as LREADY# when lready_oe_l is asserted.
lready_oe_l OUT This signal is the active-low output enable for the local bus LREADY# signal.
lbterm_o_l OUT This signal should normally be driven onto the local bus as LTERM# when lbterm_oe_l is asserted.
lbterm_oe_l OUT This signal is the active-low output enable for the local bus LBTERM# signal.
ld_oe_l OUT When this active-low signal is asserted, the user application should drive the local data bus, which is LD on models with a nonmultiplexed local bus and LAD on models with a multiplexed local bus.
eld_oe OUT This signal is an active high, early version of ld_oe_l. Functionally, ld_oe_l is obtained by inverting this signal and registering it in a flip-flop. Applications requiring the best possible clock-to-output time for the LD or LAD bus can generate their own output enables using this signal.
ready IN This signal informs the PLXDSSM module that the user application is ready to transfer data. Asserting ready causes lready_o_l to be asserted on the next cycle, assuming that a Direct Slave transfer is in progress.
stop IN This signal informs the PLXDSSM module that the user application wishes to terminate the current transfer. Assuming that a Direct Slave transfer is in progress, asserting stop may or may not cause lbterm_o_l to be asserted on the next cycle, depending on whether or not ready has already been asserted.
idle OUT This signal indicates that the state machine is currently idle. idle is never asserted at the same time as decode or transfer
decode OUT This signal indicates that a new Direct Slave transfer has started, and that the user application should perform address decoding based upon a registered version of the local bus address. It is a single cycle pulse that occurs one cycle after qlads is asserted. decode also indicates that PLXDSSM is now sensitive to the ready and stop signals.
write OUT This signal indicates whether the current Direct Slave transfer is a read (0) or a write (1). It changes only on cycles when qlads is asserted.
transfer OUT This signal indicates that data is being transferred in the current cycle, and mirrors lready_o_l (except that it is active high, whereas lready_o_l is active low). Clock enables for data registers are typically derived from this signal.

Further explanation of the relationship between the ready, stop, lready_o_l and lbterm_o_l signals is warranted. The following rules govern their behavior:

  1. ready and stop are ignored by PLXDSSM when no Direct Slave transfer is in progress. The earliest that ready and stop are checked is when decode is asserted.
  2. If a Direct Slave transfer is in progress, asserting ready will result in the assertion of lready_o_l on the next clock cycle.
  3. Once lready_o_l is asserted by PLXDSSM, it cannot be asserted until the current Direct Slave transfer ends. Thus, ready can be pulsed or held asserted.
  4. If a Direct Slave transfer is in progress, and stop is asserted before ready is asserted, PLXDSSM will remember that stop has been asserted even if stop is deasserted before ready is subsequently asserted. Once ready is asserted, PLXDSSM will assert both lready_o_l and lbterm_o_l on the next cycle. stop can be pulsed or held asserted.
  5. If a Direct Slave transfer is in progress, and stop is asserted coincident with, or after ready, PLXDSSM will assert lbterm_o_l on the next cycle.

It follows from these rules that when using PLXDSSM, LREADY# cannot be asserted and then deasserted in the middle of a transfer - the proper way to make the local bus master wait is to terminate the burst, rather than attempt to hold it off by deasserting LREADY#. In some applications, this has the advantage of giving other local bus masters a chance to utilise the bus instead of wasting cycles, increasing bus efficiency.

In very simple applications, ready and stop may simply be tied high, so that the application never permits bursting on the local bus and all local bus transfers last for exactly 3 clock cycles.

PLXDSSM state diagram

The implementation of the PLXDSSM module is a hybrid Mealy/Moore state machine:

As indicated in the state diagram,

A couple of points should be noted about this implementation:

  1. In the transition from XFER to IDLE, lready_oe_l remains asserted while lready_o_l and lbterm_o_l are deasserted. This ensures that LREADY# and LBTERM# are driven high for one cycle at the end of each transfer.
  2. For convenience, the stop signal need only be pulsed for a single clock cycle, even when the user application has not yet asserted ready. The state machine remembers that stop has been asserted via the stopping signal that is internal to the machine.
PLXDSSM timing diagrams

Here, a read and a write are shown. In the case of the write, ready is used to insert two extra wait cycles:

Notes:

  1. Asserting stop coincident with or earlier than ready always results in the transfer being terminated by LBTERM# with exactly one word of data transferred.
  2. ready and stop are ignored until PLXDSSM asserts decode.
  3. In the read transfer, ready and stop are asserted coincident with each other at the earliest possible time, namely when decode is asserted.
  4. In the write transfer, stop is asserted early, and PLXDSSM "remembers" until ready is asserted. It is not necessary to keep stop asserted until ready is asserted.

Here, a burst read is shown. ready is used to insert one extra wait cycle, and stop is asserted sometime after ready in order to terminate the burst.

Notes:

  1. Once ready has been asserted, it is not necessary to keep it asserted for the remainder of the burst. LREADY# cannot be deasserted except by ending the burst.

 


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