ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


DMA sample application

Model support

ModelSupported
ADM-XRC
ADM-XRC-P
ADM-XRC-II-Lite
ADM-XRC-II
ADM-XPL
ADM-XP
ADP-WRC-II
ADP-DRC-II
ADP-XPI
ADM-XRC-4LX
ADM-XRC-4SX
ADM-XRC-4FX
ADPE-XRC-4FX
ADM-XRC-5LX
ADM-XRC-5T1
ADM-XRC-5T2
ADM-XRC-5T2-ADV
ADM-XRC-5TZ
ADM-XRC-5T-DA1

Overview

The DMA sample application demonstrates demand-mode DMA, transferring data to the target FPGA and back into CPU memory in a "loopback" operation.

Syntax
dma [options ...]
Options

Option Argument type Meaning
-card base 10 integer ID of card to open
-index base 10 integer Index of card to open
-lclk real number Local bus clock frequency to use, in MHz (default 33.0)
-size base 10 integer Size of data blocks to transfer, in bytes; must be a multiple of 4 (default 65536)
-64   Operate local bus in 32-bit mode (default)
+64   Operate local bus in 64-bit mode

Description

On startup, the application performs the following steps:

  1. Loads the DDMA bitstream into the FPGA, using a DMA transfer.
  2. Creates two user-space buffers, one for the 'send' direction (CPU memory to FPGA) and one for the receive direction (FPGA to CPU memory). The API call ADMXRC2_SetupDMA is used to lock down the user-space buffers in physical memory.
  3. Creates a 'sender' thread, which performs demand-mode DMA transfers from the host to the FPGA, using the host-to-FPGA DMA buffer.
  4. Creates a 'receiver' thread, which performs demand-mode DMA transfers from the FPGA to the host, using the FPGA-to-host DMA buffer. This thread also performs some simple checks for correctness on the received data.

Once initialized, the application enters a loop where it expects a string to be entered by the user. Entering anything but "q" (including an empty string) causes the current data transfer counts to be displayed, and entering "q" causes the application to clean up and then terminate.

Clean up consists of terminating the threads created on startup, unlocking the user-space buffers using the ADMXRC2_UnsetupDMA API call, and frees the user-space buffers.

FPGA Design

Normally, this application uses the DDMA sample FPGA design (Verilog, VHDL). However, if the +64 option is specified on the command line, the DDMA64 sample FPGA design (Verilog, VHDL) is used instead. It is important to note that when the 64-bit version is used, the application does nothing different apart from configuring the FPGA local bus space to operate in 64-bit mode (see ADMXRC2_SetSpaceConfig) and specifying 64-bit operation when calling ADMXRC2_BuildDMAModeWord.

 


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