ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


Running the Xilinx ISE tools

When building an FPGA bitstream that targets an ADM-XRC series card, certain options must be passed to the Xilinx tools. The following table describes the options that should be used with the ISE 10.1i SP3 toolset:

Tool Command-line option Project Navigator option When to apply
MAP -pr b This option is available via the properties for the "Map" process:

Pack I/O Registers/Latches into IOBs = For Inputs and Outputs
Use this to achieve best IOB setup time and clock-to-output times by allowing MAP to pack eligible flip-flops into IOBs. In rare cases where this is not desirable, this behaviour can be overriden by attributes embedded in a design, or by IOB = FALSE constraints in a .UCF file.
MAP Virtex/-E/-EM:
-k 6

Virtex-II/-II Pro:
-k 8

Virtex-4:
-k 8

Virtex-5:
do not use*
This option is available via the properties for the "Map" process:

Virtex/-E/-EM:
Map To Input Functions = 6

Virtex-II/-II Pro:
Map To Input Functions = 8

Virtex-4:
Map To Input Functions = 8

This option causes MAP to generate functions of the maximum number of variables when possible. Although it increases the runtime of MAP, it generally improves quality of results.

* Note that this option is disabled in versions of the Xilinx ISE tools later than 10.1i, and thus Alpha Data no longer recommends applying it for Virtex-5 devices.
MAP -timing This option is available via the properties for the "Map" process:

Perform Timing-Driven Packing and Placement = True
This option causes MAP to use timing constraints from the .UCF file (or those embedded in a design when mapping a design. It increases the runtime of MAP but generally improves quality of results significantly.

Note that this option does not apply to the Virtex/-E/-EM architecture.
MAP -ol high This option is available via the properties for the "Map" process:

Map Effort Level = High
This option causes MAP to spend extra time mapping a design. It increases the runtime of MAP but generally improves quality of results significantly.

Note that this option does not apply to the Virtex/-E/-EM architecture.
PAR -ol high This option is available via the properties for the "Place & Route" process:

Place & Route Effort Level (Overall) = High
This option causes PAR to spend extra time both on the placement phase and the routing phase. It increases the runtime of PAR but generally improves quality of results significantly.
BITGEN -g drivedone:yes This option is available via the properties for the "Generate Programming File" process:

Drive Done Pin High = True
This option causes the bitstream to be generated such that the DONE pin is driven high (as opposed to floating), once configuration is completed. This option should be used for all bitstreams that target Alpha Data reconfigurable computing cards.
BITGEN -g unusedpin:pullnone This option is available via the properties for the "Generate Programming File" process:

Unused IOB Pins = Float
This option prevents unused pins from being pulled up or pulled down, and should be used for all bitstreams that target Alpha Data reconfigurable computing cards.
BITGEN -g compress This option is available via the properties for the "Generate Programming File" process:

Enable BitStream Compression = True
This option enables compression of the bitstream, which generally reduces the size of a .BIT file. It can be applied to Virtex and later architectures.

Tips for running the Xilinx tools

  1. When running PAR in ISE 4.2i or later, check that PAR reports the expected number of LOC'ed IOBs. Early on during the execution of PAR, you should see a message of the form:
    Device utilization summary:
    
       Number of External GCLKIOBs         1 out of 4      25%
       Number of External IOBs            45 out of 404    11%
          Number of LOCed External IOBs   45 out of 45    100%
    
       Number of SLICEs                 2612 out of 6912   38%
    
       Number of GCLKs                     1 out of 4      25%
       Number of TBUFs                   320 out of 7104    5%
    

    Generally, "Number of LOCed External IOBs" should be 100%. If not, it implies that one or more IOBs will be placed on arbitrary pins, which may cause problems. The .PAD file, which is produced along with the routed .NCD file, can be used to find out which I/O signals do not have location constraints.

  2. The following Xilinx answer explains that Project Navigator in ISE 5.1i does not display the "Active pullup" option in the properties for "Generate Programming File":
  3. Answer Record #15812: 5.1i Project Navigator - The "DriveDone" startup option for Virtex-II devices is not present

    A workaround for this issue is given by the following Xilinx answer:

    Answer Record #11088: 5.1i ISE- How do I specify advanced command line options in the Project Navigator GUI? (An attribute or option is not available in the GUI)

    This answer can be summarised as follows:

    1. In Windows, create or set the environment variable XIL_PROJNAV_BITGEN_OPTION, whose value is 1.
    2. Start Project Navigator.
    3. Select "Edit->Preferences" from the Project Navigator main menu.
    4. In the "Preferences" dialog, click on the "Processes" tab.
    5. Set "Property Display Level" to "Advanced".
    6. Click "Ok" to dismiss the "Preferences" dialog.
    7. Right click on "Generate Programming File" in the "Processes for Current Source" panel.
    8. Select "Properties".
    9. Click on the "General Options" tab. You should now see a text field entitled "Other Bitgen Command Line Options".
    10. Enter "-g drivedone:yes" in the "Other Bitgen Command Line Options" field.

 


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