ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


Tips for local bus interface design

The following tips may help designers new to the local bus protocol:

  1. Beware of unintentionally permitting bursting in your FPGA design. Some platforms can generate PCI reads and writes that result in bursts on the local bus, while others cannot. If your FPGA design cannot handle bursting on the local bus, it must prevent bursting or risk failing unexpectedly on certain platforms. See tip 2 below.
  2. The simplest way to prevent your FPGA design bursting on the local bus is to always assert LBTERM# along with LREADY#.
  3. It is not unnecessary to support bursting over the entire region of local bus space that your design uses. For instance, if you have implemented (a) a set of registers in one region and (b) a memory region, it may not be worthwhile going to the effort of supporting bursting in the register region, as typically the host is performing random accesses to the registers rather than performing bulk data transfer. However, designing the memory region to support bursting is probably worthwhile, as it is likely to be used for bulk data transfer. See tip 2 above.
  4. Latch the local bus address on the rising edge of LCLK when LADS# is asserted, and then increment the address internally within the FPGA each time you assert LREADY#. Use of an address generated within the FPGA as opposed to taking the address combinatorially from the LA pins can make it easier to meet timing specifications when operating LCLK at a high frequency.
  5. LBTERM# and LREADY# should not be continuously driven by the FPGA, as on some models in the ADM-XRC range there may be other slaves on the local bus. These signals should be driven only when the FPGA has positively decoded the address following the assertion of LADS#.
  6. At the end of a cycle, ensure that the FPGA drives LBTERM# and LREADY# high for a cycle or half of a cycle before being tristated. This will prevent problems due to these signals being resistively pulled up at too slow a rate. The plxdssm module used by many of the sample FPGA designs in the SDK does this.
  7. LBTERM# implies ready. In other words, assertion of LBTERM# serves to transfer the current word of data and terminate the burst. Put another way, in an application where bursting is not required, LREADY# need never be asserted while LBTERM# can serve as the "ready" signal.
  8. The normal termination condition for a burst is "(LREADY# = 0 and LBLAST# = 0) or LBTERM# = 0".
  9. Unlike a PCI bus burst, there is no mechanism for terminating a local bus burst without transferring any data. When a burst is initiated, at least one word of data must be transferred.

 


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