ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data
In a constant address mode DMA transfer, the local bus address that is presented on LA or LAD is held constant for the entire DMA transfer. This is useful for accessing a register that is actually the head or tail of a FIFO memory that is mapped at a particular local bus address. Instead of the local bus address incrementing automatically, it remains constant, both during a burst and from one local bus burst to the next. Note that this is completely unrelated to PCI addressing, as the PCI specification does not allow for constant PCI addressing.
Constant address mode may be freely mixed with the other DMA modes, such as demand mode and LEOT mode.
To use LEOT mode, the host must specify ADMXRC2_DMAMODE_FIXEDLOCAL in a call to ADMXRC2_BuildDMAModeWord. The mode word that includes constant address mode can then be supplied in a call to ADMXRC2_DoDMA and ADMXRC2_DoDMAImmediate.
This following topics illustrate the local bus protocol when constant address mode is used:
Constant address mode in local bus with nonmultiplexed address/data
Constant address mode in local bus with multiplexed address/data
Tracking the local bus address during a burst
Here, the local bus address is constant throughout each burst and constant from one burst to the next.
Here, the local bus address is implicitly constant throughout each burst and constant from one burst to the next.
At first glance, it would appear that in a local bus with multiplexed address/data, there is no way to know whether or not constant local address mode is in use, since the address is presented on LAD only in the address phase. However, a designer can simply define some conventions that are observed by both the FPGA design and the application software on the host; for example:
Such conventions are equally applicable to a local bus with nonmultiplexed data. Although the local bus address is provided on the LA signal throughout a burst, using it within the FPGA is discouraged because it may be difficult to meet timing constraints at higher frequencies of the local bus clock. A far better method is to capture the local bus address internally into a loadable counter on the assertion of LADS#, and increment it when a word of data is transferred AND the current burst is known use an incrementing address. The following circuit illustrates this technique:
The output of the circuit is the current local bus address, ie. a mirror of LA, with the advantage of having far better timing margins associated with it. It does, however, require that the application software running on the host and the FPGA design agree about how to distinguish between a constant address mode burst and an incrementing address mode burst.
For a 64-bit wide local bus, instead of loading the counter with LA[23:2] or LAD[31:2], simply use LA[23:3] or LAD[31:3].