ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


ITest sample VHDL FPGA design

Model support

Location

Synopsis

FPGA space usage

Source files

Project Navigator files

Modelsim scripts

Model support

ModelSupported
ADM-XRC
ADM-XRC-P
ADM-XRC-II-Lite
ADM-XRC-II
ADM-XPL
ADM-XP
ADP-WRC-II
ADP-DRC-II
ADP-XPI
ADM-XRC-4LX
ADM-XRC-4SX
ADM-XRC-4FX
ADPE-XRC-4FX
ADM-XRC-5LX
ADM-XRC-5T1
ADM-XRC-5T2 / ADM-XRC-5T2-ADV
ADM-XRC-5TZ
ADM-XRC-5T-DA1

Note: the ADM-XRC-5T2-ADV version of this design uses the same source files and bitstreams as the ADM-XRC-5T2, so separate files are not included within this SDK.

Location
$ADMXRC_SDK4/fpga/vhdl/itest
Synopsis

The ITest FPGA design implements logic for generating FPGA interrupts on the host. The scheme used is explained in application note AN-XRC06, which can be found in the doc/ directory of this SDK. The ITest sample application shows how to capture and handle FPGA interrupts on the host.

FPGA Space Usage

The design implements several registers for generating and acknowledging interrupts.

Interrupt Mask register (IMASK, local bus address 0x0)
Bits Mnemonic Type Function
31:0 MASK R/W Bit vector that unmasks or masks one of 32 interrupt sources in the FPGA. A '1' in a bit position masks (disables) the corresponding interrupt source.

The IMASK register allows individual interrupt sources to be enabled (unmasked) or disabled (masked). A disabled (masked) interrupt source cannot generate a local bus interrupt via the FINTI# signal.

Interrupt Status register (ISTAT, local bus address 0x4)
Bits Mnemonic Type Function
31:0 STAT R/W1C When read, returns a bit vector that indicates which of the 32 interrupt sources within the FPGA are active. A '1' in a particular bit position indicates that the corresponding interrupt source is active.
When written, a '1' in a particular bit position sets the corresponding interrupt source to inactive.

The ISTAT register indicates which of 32 interrupt sources in the FPGA are active. If an interrupt is active, a '1' will be read in the corresponding bit position of ISTAT, regardless of whether it is enabled or disabled via IMASK. Writing to a '1' to a particular bit position sets the corresponding interrupt to inactive.

Interrupt Arm register (IARM, local bus address 0x8)
Bits Mnemonic Type Function
31:0 n/a WO Writing to this register forces the FINTI# signal high for one clock cycle.

The IARM register must be used to 'rearm' the edge-sensitive FINTI# signal. Writing to IARM forces FINTI# high for one cycle. Consider the following sequence of events:

  1. FPGA interrupt source 0 becomes active; FINTI# transitions low.
  2. Host interrupt handler executes, and samples ISTAT, determining that interrupt source 0 is active.
  3. FPGA interrupt source 1 becomes active.
  4. Host interrupt handler takes whatever action is necessary to make interrupt source 0 inactive, and finishes.
  5. FINTI# does NOT transition high, because interrupt source 1 is still active.

Unfortunately, the host did not see interrupt source 1 become active. As far as it is concerned, no more interrupts have arrived; yet interrupt source 1 is now active and will not be handled, as FINTI# is still low. Note that FINTI# is an edge-triggered signal. The solution is simply for the host's interrupt handler to write to IARM just before exiting:

  1. FPGA interrupt source 0 becomes active; FINTI# transitions low.
  2. Host interrupt handler executes, and samples ISTAT, determining that interrupt source 0 is active.
  3. FPGA interrupt source 1 becomes active.
  4. Host interrupt handler takes whatever action is necessary to make interrupt source 0 inactive.
  5. Host interrupt handler writes a dummy value to IARM, and finishes.
  6. FINTI# transitions high for one cycle then low again since interrupt source 1 is still active.

At this point, the host will be interrupted again, and notice that interrupt source 1 is active.

Interrupt Test register (TEST, local bus address 0xC)
Bits Mnemonic Type Function
31:0 TEST WO Writing a 1 to a particular bit of this register makes the corresponding interrupt source active.

The TEST register can be used to test the interrupt handler on the host. By writing a 1 to a particular bit position, the corresponding interrupt source is set active.

Count register (COUNT, local bus address 0x10)
Bits Mnemonic Type Function
31:0 NCYCLE R/W This register counts local bus clock (LCLK) cycles when ISTAT[0] is '1'. When ISTAT[0] is '0', it may be written in order to initialize its value.

The COUNT register can be used to measure interrupt response time. It can be initialized to zero when ISTAT[0] is '0', and increments when ISTAT[0] is '1'.

Source files

For a list of the VHDL source files, refer to the appropriate XST project file, as referenced in the following table:

Model XST script file XST project file UCF file
ADM-XRC with Virtex itest-xrc-v.scr itest-xrc-v.prj itest-xrc.ucf
ADM-XRC with Virtex-E itest-xrc-ve.scr itest-xrc-ve.prj itest-xrc.ucf
ADM-XRC-P with Virtex itest-xrcp-v.scr itest-xrcp-v.prj itest-xrcp.ucf
ADM-XRC-P with Virtex-E itest-xrcp-ve.scr itest-xrcp-ve.prj itest-xrcp.ucf
ADM-XRC-II-Lite itest-xrc2l-v2.scr itest-xrc2l-v2.prj itest-xrc2l.ucf
ADM-XRC-II itest-xrc2-v2.scr itest-xrc2-v2.prj itest-xrc2.ucf
ADM-XPL itest-xpl-v2p.scr itest-xpl-v2p.prj itest-xpl.ucf
ADM-XP itest-xp-v2p.scr itest-xp-v2p.prj itest-xp.ucf
ADP-WRC-II itest-wrc2-v2.scr itest-wrc2-v2.prj itest-wrc2.ucf
ADP-DRC-II itest-drc2-v2.scr itest-drc2-v2.prj itest-drc2.ucf
ADP-XPI itest-xpi-v2p.scr itest-xpi-v2p.prj itest-xpi.ucf
ADM-XRC-4LX itest-xrc4lx-v4lx.scr itest-xrc4lx-v4lx.prj itest-xrc4lx.ucf
ADM-XRC-4SX itest-xrc4sx-v4sx.scr itest-xrc4sx-v4sx.prj itest-xrc4sx.ucf
ADM-XRC-4FX with 4VFX100 itest-xrc4fx-v4fx.scr itest-xrc4fx-v4fx.prj itest-xrc4fx-4vfx100.ucf
ADM-XRC-4FX with 4VFX140 itest-xrc4fx-v4fx.scr itest-xrc4fx-v4fx.prj itest-xrc4fx-4vfx140.ucf
ADPE-XRC-4FX with 4VFX100 itest-xrce4fx-v4fx.scr itest-xrce4fx-v4fx.prj itest-xrce4fx-4vfx100.ucf
ADPE-XRC-4FX with 4VFX140 itest-xrce4fx-v4fx.scr itest-xrce4fx-v4fx.prj itest-xrce4fx-4vfx140.ucf
ADM-XRC-5LX itest-xrc5lx-v5lx.scr itest-xrc5lx-v5lx.prj itest-xrc5lx.ucf
ADM-XRC-5T1 with FXT itest-xrc5t1-v5fxt.scr itest-xrc5t1-v5fxt.prj itest-xrc5t1-5vfxt.ucf
ADM-XRC-5T1 with LXT itest-xrc5t1-v5lxt.scr itest-xrc5t1-v5lxt.prj itest-xrc5t1.ucf
ADM-XRC-5T1 with SXT itest-xrc5t1-v5sxt.scr itest-xrc5t1-v5sxt.prj itest-xrc5t1.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with FXT itest-xrc5t2-v5fxt.scr itest-xrc5t2-v5fxt.prj itest-xrc5t2-5vfxt.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with LXT itest-xrc5t2-v5lxt.scr itest-xrc5t2-v5lxt.prj itest-xrc5t2.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with SXT itest-xrc5t2-v5sxt.scr itest-xrc5t2-v5sxt.prj itest-xrc5t2.ucf
ADM-XRC-5TZ with FXT itest-xrc5tz-v5fxt.scr itest-xrc5tz-v5fxt.prj itest-xrc5tz-5vfxt.ucf
ADM-XRC-5TZ with LXT itest-xrc5tz-v5lxt.scr itest-xrc5tz-v5lxt.prj itest-xrc5tz.ucf
ADM-XRC-5TZ with SXT itest-xrc5tz-v5sxt.scr itest-xrc5tz-v5sxt.prj itest-xrc5tz.ucf
ADM-XRC-5T-DA1 with FXT itest-xrc5tda1-v5fxt.scr itest-xrc5tda1-v5fxt.prj itest-xrc5tda1-5vfxt.ucf
ADM-XRC-5T-DA1 with LXT itest-xrc5tda1-v5lxt.scr itest-xrc5tda1-v5lxt.prj itest-xrc5tda1.ucf
ADM-XRC-5T-DA1 with SXT itest-xrc5tda1-v5sxt.scr itest-xrc5tda1-v5sxt.prj itest-xrc5tda1.ucf

Project Navigator files

Project Navigator projects can be found in the projnav directory as follows:

Model Project Navigator project file
ADM-XRC projnav/xrc/<device>
ADM-XRC-P projnav/xrcp/<device>
ADM-XRC-II-Lite projnav/xrc2l/<device>
ADM-XRC-II projnav/xrc2/<device>
ADM-XPL projnav/xpl/<device>
ADM-XP projnav/xp/<device>
ADP-WRC-II projnav/wrc2/<device>
ADP-DRC-II projnav/drc2/<device>
ADP-XPI projnav/xpi/<device>
ADM-XRC-4LX projnav/xrc4lx/<device>
ADM-XRC-4SX projnav/xrc4sx/<device>
ADM-XRC-4FX projnav/xrc4fx/<device>
ADPE-XRC-4FX projnav/xrce4fx/<device>
ADPE-XRC-4FX projnav/xrce4fx/<device>
ADM-XRC-5LX projnav/xrc5lx/<device>
ADM-XRC-5T1 projnav/xrc5t1/<device>
ADM-XRC-5T2
ADM-XRC-5T2-ADV
projnav/xrc5t2/<device>
ADM-XRC-5TZ projnav/xrc5tz/<device>
ADM-XRC-5T-DA1 projnav/xrc5tda1/<device>

Modelsim scripts

Example Modelsim-compatible script files for simulating this design are provided. Refer to the following table for the appropriate command line for a particular model:

Model Shell command
ADM-XRC vsim -do "do itest.do"
ADM-XRC-P vsim -do "do itest.do"
ADM-XRC-II-Lite vsim -do "do itest.do"
ADM-XRC-II vsim -do "do itest.do"
ADM-XPL vsim -do "do itest-xpl.do"
ADM-XP vsim -do "do itest-xpl.do"
ADP-WRC-II vsim -do "do itest-wrc2.do"
ADP-DRC-II vsim -do "do itest-wrc2.do"
ADP-XPI vsim -do "do itest-xpi.do"
ADM-XRC-4LX vsim -do "do itest-xrc4lx.do"
ADM-XRC-4SX vsim -do "do itest-xrc4lx.do"
ADM-XRC-4FX vsim -do "do itest-xrc4fx.do"
ADPE-XRC-4FX vsim -do "do itest-xrce4fx.do"
ADM-XRC-5LX vsim -do "do itest-xpl.do"
ADM-XRC-5T1 vsim -do "do itest-xpl.do"
ADM-XRC-5T2
ADM-XRC-5T2-ADV
vsim -do "do itest-xpl.do"
ADM-XRC-5TZ vsim -do "do itest-xpl.do"
ADM-XRC-5T-DA1 vsim -do "do itest-xpl.do"

 


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