ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


The ddrsdram_port component

Overview

HDL source code

Parameters

Signals

Row / column address selection

Performance

Overview

The ddrsdram_port component is part of the memif package and implements an interface to a bank of DDR SDRAM memory. This component follows the generic user interface for memory ports, but also has a few additional parameters and sideband signals, as shown in the following figure:

HDL source code

Projects making use of this component must include all of the following source files (relative to root of SDK installation):

fpga/vhdl/chipscope/src/ilap_pkg.vhd
fpga/vhdl/chipscope/src/ilacombo_sim.vhd
fpga/vhdl/common/memif/memif_pkg.vhd
fpga/vhdl/common/memif/memif_int_pkg.vhd
fpga/vhdl/common/memif/memif_def_synth.vhd OR fpga/vhdl/common/memif/memif_def_sim.vhd
fpga/vhdl/common/memif/cmd_fifo.vhd
fpga/vhdl/common/memif/ddrsdram/ddrsdram_clkfw.vhd
fpga/vhdl/common/memif/ddrsdram/ddrsdram_ctrl.vhd
fpga/vhdl/common/memif/ddrsdram/ddrsdram_data.vhd
fpga/vhdl/common/memif/ddrsdram/ddrsdram_data_dqs.vhd
fpga/vhdl/common/memif/ddrsdram/ddrsdram_dqs.vhd
fpga/vhdl/common/memif/ddrsdram/ddrsdram_dm.vhd
fpga/vhdl/common/memif/ddrsdram/ddrsdram_init.vhd
fpga/vhdl/common/memif/ddrsdram/ddrsdram_port.vhd

If synthesizing, the file fpga/vhdl/common/memif/memif_def_synth.vhd must be included. If simulating, the file fpga/vhdl/common/memif/memif_def_sim.vhd must be included instead.

Parameters

Name Type Function Note
a_width natural Width in bits of the port logical address, a. 4
auto_train boolean If true, the memory port automatically trains itself after reset is deasserted. If false, the memory port does not train itself. This parameter has a default value of true, and in normal usage an application should rely on the default value, and not map it to any particular value.  
d_width natural Width in bits of the port data in and out, d and q respectively. 3
pinout ddrsdram_pinout_t This value specifies the physical configuration of the memory port. For convenience, an application may map it to one of the predefined constants.  
ra_width natural Width in bits of the memory device address bus, ra. 1
rc_width natural Width in bits of the memory device control bus, rc. 2
rd_width natural Width in bits of the memory device data bus, rd. 3
tag_width natural Width in bits of the tag in and out, tag and qtag respectively.  
timing ddrsdram_timing_t This value specifies the timing of the memory port. For convenience, an application may map it to one of the predefined constants.  

Notes:

  1. The memory device address bus, ra, is composed of two fields in this memory port, with the widths of each field specified by the num_addr_bits and num_bank_bits of the pinout parameter. Therefore, ra_width is the sum of these two values. The following figure illustrates this for the case where num_addr_bits = 13 and num_bank_bits = 2:

    Note that ra_width and pinout are properties of the printed circuit board, indicating how many wires are physically present. On the other hand, the DDR SDRAM devices actually fitted to the printed circuit board may have less pins connected. The purpose of the row, col, bank and pbank signals is to specify at runtime the properties of the DDR SDRAM devices actually in use.
  2. The memory device control bus, rc, is composed of various fields in this memory port, with the widths of certain fields specified by the pinout and rd_width parameters. The following figure illustrates an example that puts rc_width at 17:

    The order of the fields within rc is always the same; only the field widths may differ from one model to another.
  3. The rd_width parameter is the number of physical DQ wires making up the data bus of the DDR SDRAM bank. This memory port transfers two words of data on the DQ wires for each command entered via the ce signal. Accordingly, the d_width parameter, which is the width of d and q, is typically specified by the user application as being twice rd_width. However, other values can be passed for d_width:
  4. The a_width parameter is the width of the logical address bus, a. Generally, it must be sufficiently wide to be able to address all of the memory in a DDR SDRAM bank. Hence, the required value of a_width depends on what memory devices are actually in use. As an example, consider two physical banks of DDR SDRAM devices that use 13 row bits, 10 column bits and 2 internal bank address bits. The number of address bits is:

    13 (row address bits) +
    10 (column address bits) +
    2 (internal bank address bits) +
    1 (2 physical banks / CS# pins) =

    26

    We must now subtract 1, because "logical" memory locations are twice as wide as the physical memory locations, due to transferring two words on the DQ pins for every command entered on ce. Hence a_width for this configuration should be at least 25. When a_width is larger than actually required, the top few unused bits of a are ignored by the memory port. In practice, one should determine the value of a_width assuming that the largest possible memory devices are in use.
Signals

The signals of this interface to and from the user application are as follows:

Signal Type Function Note
a in Logical address

User code must place a valid address on a when it asserts ce. Since a memory port effectively represents a memory device as a linear array of words of width d_width, this address is a logical address, rather than anything resembling what one might see on the ra bus.
 
bank in Bank address width select (sideband signal)

This input selects number of internal bank address bits for the DDR SDRAM devices in use:
00 => no internal bank address bits
01 => 1 internal bank address bits
10 => 2 internal bank address bits
11 => 3 internal bank address bits
6, 8
be in Byte enables to memory

User code must place valid byte enables on be whenever a write command is entered (ce and w both asserted). A logic 1 in a given bit of be means that the corresponding byte within be will be written to memory, while a zero means that the corresponding byte will not be written to memory.
 
ce in Command entry

User code asserts this signal to enter a new read or write command into the memory port. When asserted, a and w must be valid. When asserted along with w, tag must also be valid.

User code must not assert ce when ready is deasserted.

Other than that, there are no restrictions on how few or how many clock cycles ce can remain asserted. It can be pulsed for single clk0 cycles, or asserted for many clk0 cycles (ready permitting).

The address, byte enables, tag etc. of a command need not bear any relationship to that of the previous command, but refer to the section below for a discussion of how to maximize performance.
 
clk0 in Clock for user interface

All other signals except rst are synchronous to clk0.
7
clk90 in High speed clock, phase 90

This clock must be the same frequency as clk0 but lagging by 90 degrees.
7
clk180 in High speed clock, phase 180

This clock must be the same frequency as clk0 but lagging by 180 degrees.
7
clk270 in High speed clock, phase 270

This clock must be the same frequency as clk0 but lagging by 270 degrees.
7
col in Column address width select (sideband signal)

This input selects the number of column address bits to use. Along with the row input, it specifies the row/column geometry of the DDR SDRAM device, as defined here.
6, 8
d in Data to memory

User code must place valid data on d whenever a write command is entered (ce and w both asserted).
 
pbank in Physical bank select (sideband signal)

This input selects the number of physical banks (chip-selects) in use for the DDR SDRAM devices:
00 => 1 physical bank / 1 CS#
01 => 2 physical bank / 2 CS#
10 => 4 physical bank / 4 CS#
11 => 8 physical bank / 8 CS#
6, 8
q out Data from memory

When valid is asserted by the memory port (as a result of a read command), q reflects the data read from memory.
 
qtag out Tag out

When valid is asserted by the memory port (as a result of a read command), qtag reflects the tag value that was assocated with that read command.
 
ready out Port ready

When the memory port asserts ready, user code is permitted to assert ce. Certain types of memory port may unconditionally assert ready, whereas other types of memory port may sometimes deassert ready depending on several factors.

For example, a DDR SDRAM port is capable of buffering a certain number of commands internally, but if its command buffer is filled while it executes a refresh cycle, it will deassert ready.
 
regd in Registered / unregistered select (sideband signal)

This input selects whether the memory port expects registered DDR SDRAM memory or unregistered DDR SDRAM memory:

0 => unregistered
1 => registered
6, 8
row in Row address width select (sideband signal)

This input selects the number of row address bits to use. Along with the col input, it specifies the row/column geometry of the DDR SDRAM device, as defined here.
6, 8
rst in Asynchronous reset for memory port

May be tied to logic 0 if not required.
 
sr in Synchronous reset for memory port

May be tied to logic 0 if not required.
 
tag in Tag in

When user code asserts ce with w deasserted, it must also place a valid tag on the tag signal. When, as a result of the read command, the memory port asserts valid, the qtag output reflects the tag value originally passed. This is intended to facilitate sharing of a memory port between several data sources or data sinks, where each source or sink recognizes a particular set of tags.
 
trained (sideband signal) out Training success flag

When the memory port asserts trained, it indicates that training of the memory port was successful. When deasserted, either training is not yet complete or training was unsuccessful.
 
valid out Read data valid

When the memory port asserts valid, it does so as a result of a read command (user code asserted ce with w deasserted). When valid is asserted, both q and qtag are valid.
 
w in Write select

When user code asserts ce, it must place either a logic 1 on the w signal in order to select a write command, or 0 in order to select a read command.
 
x4 in X4 device select (sideband signal)

This input selects whether devices with 8- or 16-bit data or devices with 4-bit data are in use. Generally applicable to DIMM DDR SDRAM memory. In this version of the memory port, it must be zero.
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Notes:

  1. The delay from deassertion of reset to completion of training (trained asserted) may be as long as 350ms. This is because a large post-reset delay is used in order to ensure that the memory port properly initializes the DDR SDRAM devices that it is controlling after power-on.

    For simulation, however, the memory port uses a much smaller post-reset delay, with the result that the delay from deassertion of reset to completion of training is dominated by the time spent training. This is in the order of 150 microseconds of simulation time at a clk0 frequency of 133MHz.
  2. Certain properties of a DDR SDRAM device, such as number of row and column address bits, might not be known at the time of building an FPGA design. Therefore, this memory port allows certain properties to be specified "at runtime". An application might interrogate some Vital Product Data in order to determine the proper values to drive on the row, col, bank, and pbank signals.

    Alternatively, if the designer can guarantee that the properties of the DDR SDRAM devices are known when building the FPGA design, these signals can be driven with constant values. This has the advantage of lower slice utilization.

    In any case, for reliable operation, these signals must not change unless the memory port is idle.

    The purpose of these signals should not be confused with that of the pinout parameter. The pinout parameter specifies properties of the circuit board on which the FPGA and DDR SDRAM devices are mounted. In general, the number of physical wires on the circuit board provided for addressing the DDR SDRAM devices can be greater than the number actually used by a particular DDR SDRAM device.
  3. The phase and frequency relationships between the four clock phases are illustrated by the following figure:

    Also shown is the DDR SDRAM clock, CK. Its frequency is the same as clk0, but its phase is indeterminate.
  4. For correction operation, all sideband inputs must be static while the memory port is not idle.
  5. In this version, the x4 sideband input must be driven with a constant.

The signals of this interface to and from the memory device(s) are as follows:

Signal Type Function
ra in Memory device address bus

This bus carries address information to from the memory port to the memory device(s). For devices with a nontrivial addressing scheme, this address may be composed of various fields. These fields are bundled together into the ra bus so that, for the most part, the user application need not care what they are.

Refer to note 1 for the mapping of the ra bus to device pins.
rc inout Memory device control bus

This bus carries control signals between the memory port and the memory device(s), and is composed of various fields. These signals are bundled together into the rc bus so that, for the most part, the user application need not care what they are.

Refer to note 2 for the mapping of the rc bus to device pins.
rd inout Memory device data bus

This bus carries data between the memory port and the memory device(s). For each command entered via ce, two words are transferred on rd, which determines the relationship between the rd_width and d_width parameters. Refer to note 3 for details.

Row / column address selection

The row and col sideband inputs together determine the number address bits used for row and column addresses, as in the following table:

row[1:0] col[1:0] No. of row bits used No. of column bits used
00 00 12 8
00 01 12 9
00 10 12 10
00 11 12 11
01 00 13 9
01 01 13 10
01 10 13 11
01 11 13 12
10 00 14 10
10 01 14 11
10 10 14 12
10 11 14 13
11 00 15 11
11 01 15 12
11 10 15 13
11 11 15 14

Performance

This memory port features an internal command buffer capable of buffering about 10 commands before deasserting the ready signal. Most of the time, the rate of consumption of commands from the command buffer is at least as fast as production of new commands by the user application. Periodically, however, the memory port must refresh the DDR SDRAM devices it is controlling, which may result in an accumulated backlog of buffered commands, and deassertion of the ready signal. Certain usage patterns, such as alternating between read and write commands, may also have the same effect.

The architecture of DDR SDRAM device consists of a number of internal banks which are in turn divided into a number of pages. At any moment, a given bank may be "closed", or may have a given page "open". Opening or closing a bank takes a finite number of clock cycles. In this memory port, the following performance penalties exist for memory accesses falling into the following patterns:

Latency for read commands is nondeterministic due to the penalties described above, particularly because of the need to refresh, but the best-case latency from entry of a read command (ce asserted with w deasserted) to valid asserted is approximately 11 clk0 cycles. This can be modified somewhat by tightening or relaxing the timing as specified by the timing parameter. Worst case latencies may be computed by adding the above penalties to the best-case latency.

The optimal usage pattern for this memory port is blocks of accesses of the same type (read or write) to the same bank and page. A linearly incrementing address is an example of an optimal usage pattern. When used optimally, this memory port with 32 physical data bits (rd is 32) operating at a clk0 frequency of 133MHz can sustain approximately 1GB/s.

 


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