ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


The plxddsm component

Overview

HDL source code

Signals

Usage

Overview

NOTE: this component has been superseded by the plxddsm2 component.

The plxddsm component is part of the localbus package and provides the control mechanism for a demand-mode DMA channel in a local bus interface within an FPGA design. This component cannot be used in isolation; it cooperates with the plxdssm component in order to provide a complete local bus interface with the capability to perform demand-mode DMA.

HDL source code

Projects making use of this component must include all of the following source files (relative to root of SDK installation):

fpga/vhdl/common/localbus/localbus_pkg.vhd
fpga/vhdl/common/localbus/plxddsm.vhd

Signals

The signals of this interface to and from the user application are as follows:

Signal Type Function Note
clk in Local bus clock

This port must be driven by the clock that drives the local bus interface of the FPGA design.
 
idle out Interface idle

This status output indicates whether or not the plxddsm instance is currently handling a demand-mode DMA local bus cycle. It may be asserted for two reasons:
  1. There is no cycle in progress on the local bus.
  2. There is a cycle in progress on the local bus, but the qlads signal was not asserted at the beginning of the cycle, meaning that the FPGA determined that it was not the target of a demand-mode DMA local bus cycle.
 
lblast in LBLAST# in

This input must be driven by an active high version of the LBLAST# signal from the local bus.
 
lbterm in LBTERM# in

This input must be driven by an active high version of the LBTERM# signal from the local bus.
 
ldreq_o_l out LDREQ# out

This output must drive one of the LDREQ# pins on the local bus.
 
qlads in Qualified address strobe

This input should be pulsed for one clock cycle, when a local bus cycle begins. This signal is typically generated by qualifying the LADS# signal by simple address decoding along with the corresponding LDACK# signal. In most cases, the FHOLDA signal is also used.
 
ready in Data ready

The user application should assert this signal when it is ready to transfer data during a local bus cycle. This signal should be the same as the ready signal that is input to the associated plxdssm instance.
 
request in Request demand-mode DMA local bus cycle from PCI-to-local bus Bridge

The user application should assert this signal when it wishes to initiate a demand-mode DMA cycle. request may be pulsed for as little as one clock cycle; such a pulse will result in ldreq_o_l remaining asserted until the PCI-to-local bus Bridge initiates the desired demand-mode DMA local bus cycle. Alternatively, should the FPGA wish to perform many demand-mode DMA local bus cycles, request may be held asserted for an arbitary period.

The purpose of this signal is different to that of the ready signal. The ready signal permits data transfer to occur in a local bus cycle that has already started. The request signal, on the other hand, is used to control whether or not the PCI-to-local bus generates demand-mode DMA local bus cycles.

Deasserting request prevents the PCI-to-local bus Bridge from generating further demand-mode DMA cycles for a given DMA channel, while asserting request allows the PCI-to-local bus Bridge to generate demand-mode DMA cycles for that DMA channel.
 
rst in Asynchronous reset

This port may be driven by an asynchronous reset for the local bus interface, or tied to logic 0 (if not required).
 
sr in Synchronous reset

This port may be driven by a synchronous reset for the local bus interface, or tied to logic 0 (if not required).
 
stop in Terminate local bus cycle

The user application should assert this signal when it wishes to terminate the current local bus cycle. This signal should be the same as the stop signal that is input to the associated plxdssm instance.
 

Usage

For each DMA channel that is to be used in demand-mode, there must be one instance of plxddsm. Each instance of plxddsm is associated with one bit of the LDACK# and LDREQ# busses. Regardless of how many instances of plxddsm are required, exactly one instance of plxdssm is also required in order to complete the local bus interface.

The following figure illustrates a plxddsm instance connected to the one and only plxdssm instance, along with connections to the local bus and backend.

There are a couple of things to note about the above example:

  1. The generation of qlads causes the plxddsm instance to ignore local bus cycles for which the FPGA is not the target, or for which are not demand-mode DMA cycles. This generally requires only the simplest of address decoders, and an expression such as
    dd_qlads(0) <= not lads_l and not ldack_l(0) and not fholda and not la(23)
    
    often suffices. The above example uses bit 0 of LDACK# to qualify LADS#, implying that DMA channel 0 is being used. If DMA channel 1 were being used, the following expression could be used instead:
    dd_qlads(1) <= not lads_l and not ldack_l(1) and not fholda and not la(23)
    
    In other words, each plxddsm instance requires its own qlads signal, which should not be same as the qlads signal for the plxdssm instance.
  2. The control logic for generating the ready and stop inputs should be that of the plxdssm instance. The ready and stop signals should be same ones that are input to the plxdssm
  3. instance.
  4. The logic for generating request depends on whether a given demand-mode DMA channel is being used to (a) read or (b) write the FPGA:
  5. To add an additional demand-mode DMA channel, everything within the shaded area of the above figure should be replicated, and a different LDACK# and LDREQ# pair chosen.

 


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