ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data
NOTE: this component supersedes the plxddsm component.
The plxddsm2 component is part of the localbus package and provides the control mechanism for a demand-mode DMA channel in a local bus interface within an FPGA design. This component cannot be used in isolation; it cooperates with the plxdssm component in order to provide a complete local bus interface with the capability to perform demand-mode DMA.
Projects making use of this component must include all of the following source files (relative to root of SDK installation):
fpga/vhdl/common/localbus/localbus_pkg.vhd
fpga/vhdl/common/localbus/plxddsm2.vhd
The signals of this interface to and from the user application are as follows:
Signal | Type | Function | Note |
burst | in | Allow bursting during demand-mode DMA local bus cycle This signal is ignored unless a local bus cycle is in progress. If this signal is asserted while a demand-mode DMA local bus cycle is in progress, ldreq_o_l remains asserted. If this signal is deasserted while a demand-mode DMA local bus cycle is in progress, ldreq_o_l is deasserted. |
1 |
clk | in | Local bus clock This port must be driven by the clock that drives the local bus interface of the FPGA design. |
|
idle | out | Interface idle This status output indicates whether or not the plxddsm2 instance is currently handling a demand-mode DMA local bus cycle. It may be asserted for two reasons:
|
|
lblast | in | LBLAST# in This input must be driven by an active high version of the LBLAST# signal from the local bus. |
|
lbterm | in | LBTERM# in This input must be driven by an active high version of the LBTERM# signal from the local bus. |
|
ldreq_o_l | out | LDREQ# out This output must drive one of the LDREQ# pins on the local bus. |
|
lready | in | LREADY# in This input must be driven by an active high version of the LREADY# signal from the local bus. |
|
qlads | in | Qualified address strobe This input should be pulsed for one clock cycle, when a local bus cycle begins. This signal is typically generated by qualifying the LADS# signal by simple address decoding along with the corresponding LDACK# signal. In most cases, the FHOLDA signal is also used. |
|
ready | in | Data ready The user application should assert this signal when it is ready to transfer data during a local bus cycle. This signal should be the same as the ready signal that is input to the associated plxdssm instance. |
|
request | in | Request demand-mode DMA local bus cycle This signal is ignored when a demand-mode DMA local bus cycle is in progress. The user application should assert this signal when it wishes to initiate a demand-mode DMA cycle. If request is asserted while no demand-mode DMA local bus cycle is in progress, plxddsm2 will assert ldreq_o_l. request should be held asserted until the requested demand-mode DMA cycle occurs, and may be held asserted over multiple demand-mode DMA cycles if desired. |
1, 2 |
rst | in | Asynchronous reset This port may be driven by an asynchronous reset for the local bus interface, or tied to logic 0 (if not required). |
|
sr | in | Synchronous reset This port may be driven by a synchronous reset for the local bus interface, or tied to logic 0 (if not required). |
Notes
This component works by snooping on demand-mode DMA local bus cycles. When no demand-mode DMA local bus cycle is in progress, plxddsm2 asserts ldreq_o_l if and only if its request input is asserted. During a demand-mode DMA local bus cycle, plxddsm2 asserts ldreq_o_l if and only if its burst input is asserted. Thus, the possible values of request and burst yield the following behaviour:
request | burst | Behavior |
0 | X | Not requesting a demand-mode DMA cycle. |
1 | 0 | Requesting a demand-mode DMA cycle, but after the demand-mode DMA cycle begins, pause the DMA transfer as early as possible by deasserting ldreq_o_l. |
1 | 1 | Requesting a demand-mode DMA cycle, and keep ldreq_o_l asserted so as not to pause the DMA transfer. |
The purpose of request and burst is to enable a data source or sink within the target FPGA to exercise control over the burst length. This is necessary when, for example, data is being sourced onto the local bus from a FIFO, and the FIFO is almost empty. FIFO underflow must be prevented by limiting the burst length of the next demand-mode DMA cycle. For a typical application where a FIFO sources data that is being read by demand-mode DMA cycles, the request and burst signals might work as follows:
Another way that the target FPGA can control burst length is via the stop signal of the plxdssm component. That signal can be used to terminate a demand-mode DMA local bus cycle (although it doesn't necessarily pause a demand-mode transfer), and together with request and burst, offers the most flexibility in controlling a demand-mode DMA transfer.
For each DMA channel that is to be used in demand-mode, there must be one instance of plxddsm2. Each instance of plxddsm2 is associated with one bit of the LDACK# and LDREQ# busses. Regardless of how many instances of plxddsm2 are required, exactly one instance of plxdssm is also required in order to complete the local bus interface.
The following figure illustrates a plxddsm2 instance connected to the one and only plxdssm instance, along with connections to the local bus and backend.
There are a couple of things to note about the above example:
dd_qlads(0) <= not lads_l and not ldack_l(0) and not fholda and not la(23)often suffices. The above example uses bit 0 of LDACK# to qualify LADS#, implying that DMA channel 0 is being used. If DMA channel 1 were being used, the following expression could be used instead:
dd_qlads(1) <= not lads_l and not ldack_l(1) and not fholda and not la(23)In other words, each plxddsm2 instance requires its own qlads signal, which should not be same as the qlads signal for the plxdssm instance.