ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


ZBT64 sample Verilog FPGA design

Model support

Location

Synopsis

FPGA space usage

Source files

Project Navigator files

Model support

ModelSupported
ADM-XRC 
ADM-XRC-P 
ADM-XRC-II-Lite 
ADM-XRC-II 
ADM-XPL 2VP20, 2VP30 only
ADM-XP 
ADP-WRC-II 
ADP-DRC-II 
ADP-XPI 
ADM-XRC-4LX 
ADM-XRC-4SX 
ADM-XRC-4FX 
ADPE-XRC-4FX 
ADM-XRC-5LX 
ADM-XRC-5T1 
ADM-XRC-5T2 / ADM-XRC-5T2-ADV 
ADM-XRC-5TZ 
ADM-XRC-5T-DA1 

Location
$ADMXRC_SDK4/fpga/verilog/zbt64
Synopsis

Note: this FPGA design has been effectively superseded by the Memory64 sample FPGA design (VHDL), since the latter is more general and supports a larger number of models and types of memory.

The ZBT64 FPGA design demonstrates how to implement a 64-bit host interface to the SSRAM in an FPGA design. The design divides the 4MB FPGA space into a lower 2MB region for register and an upper 2MB window for accessing the SSRAM. A page register is provided so that all of the SSRAM on a card is available to the host.

This example demonstrates the following:

The design accomodates pipelined or flowthrough JEDEC-compliant ZBT SSRAM devices. Some ZBT devices are capable of operating in either pipelined or flowthrough mode, depending on the level on a mode-select pin. The FPGA design therefore contains a register that selects pipelined or flowthrough operation.

The design maps the data pins of each physical SSRAM bank to the 64-bit local data bus. Currently, only the ADM-XPL is capable of operating with a 64-bit local bus. The ADM-XPL has a single 64-bit SSRAM device, and so this device's data bits can be mapped one-to-one to the local data bus bits.

The design also contains a register that selects the number of address bits in the logical SSRAM banks. Address lengths of 17, 18, 19 and 20 bits are accomodated.

The page register augments the limited address space (2MB) allotted to accessing the SSRAM. The following figure illustrates this on an ADM-XPL with a 1M x 64 ZBT SSRAM device fitted:

FPGA Space Usage

The following registers exist in the 2MB register region:

Page register (PAGE, local bus address 0x0)
Bits Mnemonic Type Function
7:0 PAGE R/W Value that augments bits [20:3] of the local bus address, when accessing the SSRAM.
31:8   MBZ  

Mode register (MODE, local bus address 0x4)
Bits Mnemonic Type Function
0 PIPELINED R/W Value that selects the mode in which to operate the ZBT SSRAM devices:
0 => flowthrough
1 => pipelined
31:1   MBZ  

Size register (SIZE, local bus address 0x8)
Bits Mnemonic Type Function
1:0 SIZE R/W Value that specifies the number of address bits in a logical SSRAM bank:
0 => 17 (128k words)
1 => 18 (256k words)
2 => 19 (512k words)
3 => 20 (1M words)
31:2   MBZ  

Information register (INFO, local bus address 0x10)
Bits Mnemonic Type Function
23:0 BANKSIZE RO Returns size, in words, of each logical SSRAM bank.
31:24 NUMBANK RO Number of logical SSRAM banks in the design.

Status register (STATUS, local bus address 0x14)
Bits Mnemonic Type Function
0 LCLK_LOCKED RO Returns '1' if the local bus clock (LCLK) DCM/DLL is currently locked.
n:1 RAMCLK_LOCKED RO If n is the number of SSRAM clock signals in the design, this register returns '1' in a particular bit if the DCM/DLL for that clock signal is currently locked. Bit 1 corresponds to SSRAM clock 0.
31:n+1   RAX  

Source files

For a list of the Verilog source files, refer to the appropriate XST project file, as referenced in the following table:

Model XST script file XST project file UCF file
ADM-XPL zbt64-xpl-v2p.scr zbt64-xpl-v2p.prj zbt64-xpl.ucf

Project Navigator files

Project Navigator projects can be found in the projnav directory as follows:

Model Project Navigator project file
ADM-XPL projnav/xpl/<device>

 


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