ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


The memif package

Overview of this package

Components

Datatypes

Constants

Generic memory port user interface

Overview

The memif package consists of a number of components providing memory ports for several types of memory device. The purpose of the memif package is twofold:

  1. To hide any complexity present in a given memory type from the user application, so that the user application may treat it as a array of randomly-accessible memory locations.
  2. To provide memory port components whose user interfaces are as similar as possible.

From the point of view of client code, the above components all present a similar interface to the user. This generic user interface is described below. The components, datatypes and constants exported by the memif package are listed in the sections below.

Components

Name Function
arbiter_2 Two port multiplexor for a memory port
arbiter_3 Three port multiplexor for a memory port
arbiter_4 Four port multiplexor for a memory port
ddr2sdram_port DDR-II SDRAM memory port, for Virtex-4 and Virtex-5
ddr2sram_port_v2 DDR-II SSRAM memory port, for Virtex-2 and Virtex-2 Pro
ddr2sram_training_v2 DDR-II SSRAM training module, for Virtex-2 and Virtex-2 Pro
ddr2sram_port_v4 DDR-II SSRAM memory port, for Virtex-4 and Virtex-5
ddrsdram_port_v2 DDR SDRAM memory port, for Virtex-2 and Virtex-2 Pro
ddrsdram_training_v2 DDR SDRAM training module, for Virtex-2 and Virtex-2 Pro
zbtsram_port ZBT SSRAM memory port, for all FPGA families

Datatypes

Name Function
ddr2sdram_pinout_t Record type that describes the physical configuration of a DDR-II SDRAM port.
ddr2sdram_timing_t Record type that describes the timing of a DDR-II SDRAM port.
ddrsdram_pinout_t Record type that describes the physical configuration of a DDR SDRAM port.
ddrsdram_timing_t Record type that describes the timing of a DDR SDRAM port.
ddr2sram_pinout_t Record type that describes the physical configuration of a DDR-II SSRAM port.
family_t Enumerated type that represents an FPGA family.
zbtsram_pinout_t Record type that describes the physical configuration of a ZBT SSRAM port.

Constants

Name
(Datatype)
Function
ddr2sdram_pinout_admxrc4fx
(ddr2sdram_pinout_t)
Pinout for an ADM-XRC-4FX DDR-II SDRAM bank.
ddr2sdram_pinout_adpexrc4fx
(ddr2sdram_pinout_t)
Pinout for an ADPE-XRC-4FX DDR-II SDRAM bank.
ddr2sdram_pinout_admxrc5lx
(ddr2sdram_pinout_t)
Pinout for an ADM-XRC-5LX DDR-II SDRAM bank.
ddr2sdram_pinout_admxrc5t1
(ddr2sdram_pinout_t)
Pinout for an ADM-XRC-5T1 DDR-II SDRAM bank.
ddr2sdram_pinout_admxrc5t2
(ddr2sdram_pinout_t)
Pinout for an ADM-XRC-5T2 / ADM-XRC-5T2-ADV DDR-II SDRAM bank.
ddr2sdram_pinout_admxrc5tda1
(ddr2sdram_pinout_t)
Pinout for an ADM-XRC-5T-DA1 DDR-II SDRAM bank.
ddrsdram_pinout_admxpl
(ddrsdram_pinout_t)
Pinout for an ADM-XPL DDR SDRAM bank.
ddrsdram_pinout_admxp
(ddrsdram_pinout_t)
Pinout for an ADM-XP DDR SDRAM bank.
ddr2sram_pinout_admxp
(ddr2sram_pinout_t)
Pinout for an ADM-XP DDR-II SSRAM bank.
ddr2sram_pinout_admxrc5t1
(ddr2sram_pinout_t)
Pinout for an ADM-XRC-5T1 DDR-II SSRAM bank.
ddr2sram_pinout_admxrc5t2
(ddr2sram_pinout_t)
Pinout for an ADM-XRC-5T2 / ADM-XRC-5T2-ADV DDR-II SSRAM bank.
ddr2sram_pinout_admxrc5tda1
(ddr2sram_pinout_t)
Pinout for an ADM-XRC-5T-DA1 DDR-II SSRAM bank.
zbtsram_pinout_admxrc
(zbtsram_pinout_t)
Pinout for an ADM-XRC ZBT SSRAM bank.
zbtsram_pinout_admxrcp
(zbtsram_pinout_t)
Pinout for an ADM-XRC-P ZBT SSRAM bank.
zbtsram_pinout_admxrc2l
(zbtsram_pinout_t)
Pinout for an ADM-XRC-II-Lite ZBT SSRAM bank.
zbtsram_pinout_admxrc2
(zbtsram_pinout_t)
Pinout for an ADM-XRC-II ZBT SSRAM bank.
zbtsram_pinout_admxpl
(zbtsram_pinout_t)
Pinout for an ADM-XPL ZBT SSRAM bank.
zbtsram_pinout_admxrc4lx
(zbtsram_pinout_t)
Pinout for an ADM-XRC-4LX ZBT SSRAM bank.
zbtsram_pinout_admxrc4sx
(zbtsram_pinout_t)
Pinout for an ADM-XRC-4SX ZBT SSRAM bank.
zbtsram_pinout_admxrc5tz
(zbtsram_pinout_t)
Pinout for an ADM-XRC-5TZ ZBT SSRAM bank.
ddr2sdram_timing_266
(ddr2sdram_timing_t)
Timing for a generic 266MHz DDR-II SDRAM device (also known as DDR533). This corresponds to a clk0 frequency of 133MHz.
ddrsdram_timing_cl25_133
(ddrsdram_timing_t)
Timing for a generic CL2.5 133MHz DDR SDRAM device (also known as DDR266 or PC2100). This corresponds to a clk0 frequency of 133MHz.

Generic user interface

In general, the memory ports can be represented as a black box as in the following figure:

The parameters of this interface are as follows:

Name Type Function
ra_width natural Width in bits of the memory device address bus, ra.

Refer to the documentation for a specific type of memory port for the details of the the relationship between ra_width and a_width.
rc_width natural Width in bits of the memory device control bus, rc.

Refer to the documentation for a specific type of memory port for details of how to specify a legal value for rc_width.
rd_width natural Width in bits of the memory device data bus, rd.

Refer to the documentation for a specific type of memory port for the details of the the relationship between rd_width and d_width.
a_width natural Width in bits of the port logical address, a.

Refer to the documentation for a specific type of memory port for the details of the the relationship between ra_width and a_width.
d_width natural Width in bits of the port data in and out, d and q respectively. Also determines the width of the byte enables, be.

Refer to the documentation for a specific type of memory port for the details of the the relationship between rd_width and d_width.
tag_width natural Width in bits of the tag in and out, tag and qtag respectively.

The signals of this interface to and from the user application are as follows:

Signal Type Function
a in Logical address

User code must place a valid address on a when it asserts ce. Since a memory port effectively represents a memory device as an array of words of width d_width, this address is a logical address, because the address that eventually appears on the ra bus may not necessarily be the same as whatever user code placed on the a bus.
be in Byte enables to memory

User code must place valid byte enables on be whenever a write command is entered (ce and w both asserted). A logic 1 in a given bit of be means that the corresponding byte within be will be written to memory, while a zero means that the corresponding byte will not be written to memory.
ce in Command entry

User code asserts this signal to enter a new read or write command into the memory port. When asserted, a and w must be valid. When asserted along with w, tag must also be valid.

User code must not assert ce when ready is deasserted.

Other than that, there are no restrictions on how few or how many clock cycles ce can remain asserted. It can be pulsed for single clk0 cycles, or asserted for many clk0 cycles (ready permitting).

The address, byte enables, tag etc. of a command need not bear any relationship to that of the previous command, but for some memory types, it may be beneficial for performance to avoid certain patterns of addressing, or to avoid frequently changing from a read command to a write command on every cycle. Performance issues are discussed in detail for each type of memory port.
clk0 in Clock for user interface

All other signals except rst are synchronous to clk0.
d in Data to memory

User code must place valid data on d whenever a write command is entered (ce and w both asserted).
q out Data from memory

When valid is asserted by the memory port (as a result of a read command), q reflects the data read from memory.
qtag out Tag out

When valid is asserted by the memory port (as a result of a read command), qtag reflects the tag value that was assocated with that read command.
ready out Port ready

When the memory port asserts ready, user code is permitted to assert ce. Certain types of memory port may unconditionally assert ready, whereas other types of memory port may sometimes deassert ready depending on several factors.

For example, a DDR-II SDRAM port is capable of buffering a certain number of commands internally, but if its command buffer is filled while it executes a refresh cycle, it will deassert ready.
rst in Asynchronous reset for memory port

May be tied to logic 0 if not required.
sr in Synchronous reset for memory port

May be tied to logic 0 if not required.
tag in Tag in

When user code asserts ce with w deasserted, it must also place a valid tag on the tag signal. When, as a result of the read command, the memory port asserts valid, the qtag output reflects the tag value originally passed. This is intended to facilitate sharing of a memory port between several data sources or data sinks, where each source or sink recognizes a particular set of tags.
valid out Read data valid

When the memory port asserts valid, it does so as a result of a read command (user code asserted ce with w deasserted). When valid is asserted, both q and qtag are valid.
w in Write select

When user code asserts ce, it must place either a logic 1 on the w signal in order to select a write command, or 0 in order to select a read command.

The signals of this interface to and from the memory device(s) are as follows:

Signal Type Function
ra in Memory device address bus

This bus carries address information to from the memory port to the memory device(s). For devices with a nontrivial addressing scheme, this address may be composed of various fields. These fields are bundled together into the ra bus so that, for the most part, the user application need not care what they are.

For example, with SDRAM devices, this bus may sometimes carry a column address, and at other times row and bank addresses. The correspondence between bits of ra and the various pins found on a given type of memory device is discussed in the documentation for that type of memory port.
rc inout Memory device control bus

This bus carries control signals between the memory port and the memory device(s), and is composed of various fields. These signals are bundled together into the rc bus so that, for the most part, the user application need not care what they are. The correspondence between bits of rc and the various pins found on a given type of memory device is discussed in the documentation for that type of memory port.
rd inout Memory device data bus

This bus carries data between the memory port and the memory device(s).

 


 Top of page