ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


MEMORYF sample application

Model support

ModelSupported
ADM-XRC
ADM-XRC-P
ADM-XRC-II-Lite
ADM-XRC-II
ADM-XPL
ADM-XP
ADP-WRC-II 
ADP-DRC-II 
ADP-XPI 
ADM-XRC-4LX
ADM-XRC-4SX
ADM-XRC-4FX
ADPE-XRC-4FX
ADM-XRC-5LX
ADM-XRC-5T1
ADM-XRC-5T2
ADM-XRC-5T2-ADV
ADM-XRC-5TZ
ADM-XRC-5T-DA1

Overview

The MemoryF sample application performs a fast, chip-driven memory test that verifies the memories on a reconfigurable computing card.

Syntax
memoryf [options ...]
Options

Option Type Meaning
-banks hexadecimal integer Bitmask of banks to test (default 0xFFFFFFFF)
-card base 10 integer ID of card to open
-index base 10 integer Index of card to open
-lclk real number Local bus clock frequency to use, in MHz (default depends upon type of card)
-mclk real number Memory clock frequency to use, in MHz (default depends upon type of card)
-refclk220   Do not enable Virtex-5 IDELAYCTRL reference clock workaround (default)
+refclk220   Enable Virtex-5 IDELAYCTRL reference clock workaround
-repeat base 10 integer Number of times to perform tests (default 1)
-64   Operate local bus in 32 bit mode (default)
+64   Operate local bus in 64 bit mode

Description

The MemoryF sample application tests all banks of on-board memory on a reconfigurable computing card. Unlike the Memory application, MemoryF performs a chip-driven memory test. The CPU initiates the test and waits for completion, but does not actively participate in the memory test. This reduces the runtime for the test by at least one order of magnitude compared to the Memory application.

When run, the MemoryF sample application commands the target FPGA to perform a consisting of the following phases:

  1. Constant 0x55 pattern written to memory, for detecting data bits stuck at 0, 1 or shorted to other signals.
  2. Constant 0xAA pattern written to memory, for detecting data bits stuck at 0, 1 or shorted to other signals.
  3. Alternating 0x55 / 0xAA pattern written to memory, for detecting data bits stuck at 0, 1 or shorted to other signals. The pattern is designed to toggle all of the data lines for a given bank at the maximum possible frequency during a burst of memory accesses.
  4. Own address pattern written to memory, for detecting address bits stuck at 0, 1 or shorted to other signals.
  5. Bit-reversed own address pattern written to memory, for detecting address bits stuck at 0, 1 or shorted to other signals.
  6. Random data written to memory, for detecting pattern-sensitive failures.

The +64 option causes the application to operate the local bus in 64-bit mode. This is valid only for models that support a 64-bit local bus.

A subset of the memory banks on a card can be tested by passing a bitmask of banks to test via the -banks option. For example, -banks 0xD would specify that only banks 0, 2 and 3 should be tested.

The local bus clock frequency used for the memory test can be specified on the command-line using the -lclk option. For example, -lclk 45 specifies a local bus clock frequency of 45 MHz. If the -lclk option is not specified on the command-line, the MemoryF application programs a sensible default frequency (for the model on which the application is run) into the local bus clock generator. For example, the default LCLK frequency when running MemoryF on an ADM-XRC-II is 66 MHz.

By default, the MemoryF application programs the MCLK clock generator to an appropriate frequency for the memory clock domain. This may be changed on the command-line using the -mclk option, although it is advisable that the user understands the relationship between the freqency at the target FPGA's MCLK pin (i.e. what is programmed into the clock generator) and the frequency of the internal clock within the FPGA. For example, with an ADM-XRC-4FX card, passing the option -mclk 210 on the command-line would result in the DDR-II SDRAM devices on the card operating at 210 MHz (DDR 420) and the memory clock domain within the target FPGA operating at 105 MHz. With an ADM-XRC-4LX card, passing the option -mclk 140 on the command-line would result in the ZBT SSRAM devices on the card operating at 140 MHz and the memory clock domain within the target FPGA also operating at 140 MHz.

FPGA Design

The MemoryF sample application normally uses the Memory sample FPGA design (VHDL), but when the +64 option is specified, it uses the Memory64 sample FPGA design (VHDL).

 


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