ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


Synplify/Synplify Pro issues

There are several issues that affect users of Synplify/Synplify Pro when rebuilding the example FPGA designs in the SDK:

  1. Bus nomenclature in netlist

    XST names busses as signal<n>, whereas Synplify names busses by default as signal[n]. This causes ngdbuild to fail if the .UCF files supplied with the SDK are used. Users of Synplify/Synplify Pro include the file synpro_bus.sdc, in the directory $ADMXRC_SDK4/vhdl/common, in their projects to make Synplify/Synplify Pro use a signal<n> nomenclature.

  2. Hierarchical separator character

    XST uses the _ (underscore) character as a hierarchy separator, whereas Synplify/Synplify Pro uses a / (forward slash) character. It is possible to work around this problem, as far as constraints in .UCF files go, by using the ? wildcard (match any single character) in the .UCF file.

  3. Hierarchical net naming in netlist

    XST names nets that are not at the top level differently to Synplify/Synplify Pro. A full description of the XST naming convention can be found in the XST user guide. Synplify Pro names net strictly according to their name and the highest hierarchy level in which that net is found. Fortunately, it is often possible to avoid needing to reference nets that are not in the top level in a .UCF file.

  4. Hierarchical primitive instance naming in netlist

    XST names certain types of primitive, for example clock buffers, according to their hierarchy level, their label and their type. Synplify/Synplify Pro names an instance strictly according to its label and hierarchy level.

 


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