ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


Generating ISE Project files

As of Xilinx ISE 7.1i, project files for Project Navigator (.ISE extension) are binary files. Furthermore, filenames are stored as absolute paths regardless of whether or not the filenames were added to the project as relative or absolute paths. For this reason, project files are in general not portable between users or workstations as different users tend do their work in different locations. In this release of the SDK, Project Navigator files are not supplied but can be generated after installation by running a script (requires ISE tools to be in user's PATH). There are several choices for the user when deciding how to run this script:

  1. Generate Project Navigator files for all sample VHDL and Verilog designs.
  2. Generate Project Navigator files for all sample VHDL designs.
  3. Generate Project Navigator files for all sample Verilog designs.
  4. Generate Project Navigator files for a specific Verilog or VHDL design.

NOTE

The scripts used to generate Project Navigator files are known to be compatible with ISE 10.1i. They will not work with any ISE version earlier than 10.1i, and are not guaranteed to work correctly with any ISE version later than 10.1i.

1. Generate Project Navigator files for all sample VHDL and Verilog designs

To generate project files for all sample designs in the SDK, both VHDL and Verilog, start a shell and issue the following commands:

cd $ADXMRC_SDK4/fpga
./projnav.bash mkproj

Because this process creates hundreds of .ISE files, it may take from minutes to hours to run to completion. The user should also verify that at least 550MB of disk space are available before entering these commands.

2. Generate Project Navigator files for all sample VHDL designs

To generate project files for all sample VHDL designs in the SDK, start a shell and issue the following commands:

cd $ADXMRC_SDK4/fpga/vhdl
./projnav.bash mkproj

Because this process creates hundreds of .ISE files, it may take from minutes to hours to run to completion. The user should also verify that at least 400MB of disk space are available before entering these commands.

3. Generate Project Navigator files for all sample Verilog designs

To generate project files for all sample Verilog designs in the SDK, start a shell and issue the following commands:

cd $ADXMRC_SDK4/fpga/verilog
./projnav.bash mkproj

Because this process creates hundreds of .ISE files, it may take from minutes to hours to run to completion. The user should also verify that at least 150MB of disk space are available before entering these commands.

4. Generate Project Navigator files for a specific VHDL or Verilog design

To generate project files for a specific sample VHDL or Verilog design, start a shell and issue the following commands:

cd $ADXMRC_SDK4/fpga/<language>/<design>
./projnav.bash mkproj

where <language> is either 'vhdl' or 'verilog', and <design> is one of the sample FPGA designs, for example 'ddma'. Because this process may create dozens of .ISE files, it may take a few minutes to run to completion and may consume up to 40 MB of disk space.

 


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