ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


The ddr2sram_port_v2 component (Virtex-II / Virtex-II Pro only)

Overview

HDL source code

Parameters

Signals

Performance

Overview

The ddr2sram_port_v2 component is part of the memif package and implements an interface to a bank of DDR-II SSRAM memory. A related component is the ddr2sram_training_v2 component, which provides infrastructure for training one or more instances of ddr2sram_port_v2. This component follows the generic user interface for memory ports, but also has a few additional parameters and sideband signals, as shown in the following figure:

HDL source code

Projects making use of this component must include all of the following source files (relative to root of SDK installation):

fpga/vhdl/common/memif/memif_pkg.vhd
fpga/vhdl/common/memif/memif_int_pkg.vhd
fpga/vhdl/common/memif/memif_def_synth.vhd OR fpga/vhdl/common/memif/memif_def_sim.vhd
fpga/vhdl/common/memif/cmd_fifo.vhd
fpga/vhdl/common/memif/ddr2sram_v2/ddr2sram_port_v2.vhd

If synthesizing, the file fpga/vhdl/common/memif/memif_def_synth.vhd must be included. If simulating, the file fpga/vhdl/common/memif/memif_def_sim.vhd must be included instead.

Parameters

Name Type Function Note
a_width natural Width in bits of the port logical address, a. 4
d_width natural Width in bits of the port data in and out, d and q respectively. 3
pinout ddr2sram_pinout_t This value specifies the physical configuration of the memory port. For convenience, an application may map it to one of the predefined constants.  
ra_width natural Width in bits of the memory device address bus, ra. 1
rc_width natural Width in bits of the memory device control bus, rc. 2
rd_width natural Width in bits of the memory device data bus, rd. 3
tag_width natural Width in bits of the tag in and out, tag and qtag respectively.  

Notes:

  1. The ra_width parameter is a property of the printed circuit board, indicating how many wires are physically present, rather than indicating how many of the ra lines are used by a particular DDR-II SSRAM device.
  2. The memory device control bus, rc, is composed of various fields in this memory port, with the widths of certain fields specified by the pinout and rd_width parameters. The following figure illustrates the fields that comprise the rc bus:

    The order of the fields within rc is always the same, but some models may lack certain fields.
  3. The rd_width parameter is the number of physical DQ wires making up the data bus of the DDR-II SSRAM bank. This memory port transfers two words of data on the DQ wires for each command entered via the ce signal. Accordingly, the d_width parameter, which is the width of d and q, is typically specified by the user application as being two times rd_width. However, other values can be passed for d_width:
  4. The a_width parameter is the width of the logical address bus, a. Generally, it must be sufficiently wide to be able to address all of the memory in a DDR-II SSRAM bank. Hence, the required value of a_width depends on what memory devices are actually in use. As an example, consider a DDR-II SSRAM device with 20 address bits. Since "logical" memory locations are two times as wide as the physical memory locations, one must subtract 1, giving a value of 19 for the minimum value of a_width. When a_width is larger than actually required, the top few unused bits of a are ignored by the memory port. In practice, one should determine the value of a_width assuming that the largest possible memory devices are in use.
Signals

The signals of this interface to and from the user application are as follows:

Signal Type Function Note
a in Logical address

User code must place a valid address on a when it asserts ce. Since a memory port effectively represents a memory device as a linear array of words of width d_width, this address is a logical address, rather than anything resembling what one might see on the ra bus.
 
be in Byte enables to memory

User code must place valid byte enables on be whenever a write command is entered (ce and w both asserted). A logic 1 in a given bit of be means that the corresponding byte within be will be written to memory, while a zero means that the corresponding byte will not be written to memory.
 
burst_len in Burst length (sideband signal)

If this input is 0, then the SSRAM devices being driven must be burst length 2 devices. If this input is 1, then the SSRAM devices being driven may be burst length 2 or burst length 4 devices.
8
ce in Command entry

User code asserts this signal to enter a new read or write command into the memory port. When asserted, a and w must be valid. When asserted along with w, tag must also be valid.

User code must not assert ce when ready is deasserted.

Other than that, there are no restrictions on how few or how many clock cycles ce can remain asserted. It can be pulsed for single clk0 cycles, or asserted for many clk0 cycles (ready permitting).

The address, byte enables, tag etc. of a command need not bear any relationship to that of the previous command, but refer to the section below for a discussion of how to maximize performance.
 
cedge (training signal) in Capture edge

This signal is normally driven directly by an instance of the component ddr2sram_training_v2, and contains information instructing ddr2sram_port_v2 how to retime the data captured from the SSRAM device using clkc0 and clkc180 into the clk0 domain.
7
clk0 in Clock for user interface

All other signals except rst are synchronous to clk0.
5
clk90 in Clock, phase 90

This clock must be the same frequency as clk0 but 90 degrees behind in phase.
5
clk180 in Clock, phase 180

This clock must the same frequency as clk0 but 180 degrees behind in phase.
5
clk270 in Clock, phase 270

This clock must the same frequency as clk0 but 270 degrees behind in phase.
5
clkc0 in Capture clock, phase 0

This clock is normally driven directly by the component ddr2sram_training_v2 and is used by ddr2sram_port_v2 to capture data read from the SSRAM device in the FPGA's IOBs.
5, 9
clkc180 in Capture clock, phase 180

This clock is normally driven directly by the component ddr2sram_training_v2 and is used by ddr2sram_port_v2 to capture data read from the SSRAM device in the FPGA's IOBs.
5, 9
d in Data to memory

User code must place valid data on d whenever a write command is entered (ce and w both asserted).
 
dll_off in DLL disable (sideband signal)

User code should drive this input with 0 for normal operation, but driving it with 1 causes the DOFF# field within rc to be asserted.
6
q out Data from memory

When valid is asserted by the memory port (as a result of a read command), q reflects the data read from memory.
 
qtag out Tag out

When valid is asserted by the memory port (as a result of a read command), qtag reflects the tag value that was assocated with that read command.
 
ready out Port ready

When the memory port asserts ready, user code is permitted to assert ce.
 
rst in Asynchronous reset for memory port

May be tied to logic 0 if not required.
 
sr in Synchronous reset for memory port

May be tied to logic 0 if not required.
 
tag in Tag in

When user code asserts ce with w deasserted, it must also place a valid tag on the tag signal. When, as a result of the read command, the memory port asserts valid, the qtag output reflects the tag value originally passed. This is intended to facilitate sharing of a memory port between several data sources or data sinks, where each source or sink recognizes a particular set of tags.
 
tstcomp (training signal) in Capture edge

This signal is normally driven directly by an instance of the component ddr2sram_training_v2, and informs the ddr2sram_port_v2 that training is complete and that normal operation can begin.
7
tstdo (training signal) in Do readback test

This signal is normally driven directly by an instance of the component ddr2sram_training_v2, and instructs the ddr2sram_port_v2 to perform a readback experiment during the training sequence.
7
tstdone (training signal) out Done readback test

This signal is normally connected directly to an instance of the component ddr2sram_training_v2, and informs the ddr2sram_training_v2 instance that the ddr2sram_port_v2 has completed a readback experiment (during the training sequence). It qualifies the tstok output.
7
tstok (training signal) out Readback test OK

This signal is normally connected directly to an instance of the component ddr2sram_training_v2, and informs the ddr2sram_training_v2 instance whether or not the most recent readback experiment was successful. It is qualified by the tstdone output.
7
valid out Read data valid

When the memory port asserts valid, it does so as a result of a read command (user code asserted ce with w deasserted). When valid is asserted, both q and qtag are valid.
 
w in Write select

When user code asserts ce, it must place either a logic 1 on the w signal in order to select a write command, or 0 in order to select a read command.
 

Notes:

  1. The phase and frequency relationships between the four clock phases are illustrated by the following figure:

    Also shown are the related clocks: the DDR-II SSRAM clock pair, K and K#, and the capture clock pair clkc0 and clkc180. Their frequencies are the same as clk0, but their phases are indeterminate with respect to clk0.
  2. For correction operation, all sideband inputs must be static while the memory port is not idle.
  3. The connections between an instance of the training module ddr2sram_training_v2 and an instance of ddr2sram_port_v2 form a private communication channel. The information carried by this channel is generally not of interest to the user, but brief descriptions of each signal in the channel are provided for information only. Training of ddr2sram_port_v2, from deassertion of reset to completion of training (tstcomp asserted) takes no more than 1 millisecond at a clk0 frequency of 133MHz.
  4. When it is known that burst length 2 devices are being used, driving the burst_len input with 0 results in fewer cycles being wasted when random reads and writes are performed in quick succession. However, driving the burst_len with 1 is "safe" in that it enables SSRAM devices of burst length 2 or 4 to be used interchangeably. Alpha Data recommends driving burst_len with 1 unless the application demands the maximum possible bandwidth from the SSRAM devices.
  5. The ddr2sram_training_v2 component works by varying the phase of the capture clocks clkc0 and clkc180 in order to find a window in which data from the SSRAM device's DQ pins can be reliably captured. Hence these clocks are the same frequency as clk0 etc. but the required phase relationship is discovered during the training sequence.

The signals of this interface to and from the memory device(s) are as follows:

Signal Type Function
ra in Memory device address bus

This bus carries address information to from the memory port to the memory device(s).
rc inout Memory device control bus

This bus carries control signals between the memory port and the memory device(s), and is composed of various fields. These signals are bundled together into the rc bus so that, for the most part, the user application need not care what they are.

Refer to note 2 for the mapping of the rc bus to device pins.
rd inout Memory device data bus

This bus carries data between the memory port and the memory device(s). For each command entered via ce, two words are transferred on rd, which determines the relationship between the rd_width and d_with parameters. Refer to note 3 for details.

Performance

This memory port features an internal command buffer capable of buffering about 10 commands before deasserting the ready signal. Most of the time, the rate of consumption of commands from the command buffer is at least as fast as production of new commands by the user application. Certain usage patterns, however, may result in a accumulated backlog in the command buffer.

There is one performance penalty in this memory port:

Latency for read commands is fairly deterministic, since the penalties described above are limited to one cycle (although these penalties may be accumulated by successive commands). The best-case latency from entry of a read command (ce asserted with w deasserted) to valid asserted is approximately 10 clk0 cycles. Worst case latencies may be computed by adding the above penalties to the best-case latency.

The optimal usage pattern for this memory port is blocks of accesses of the same type (read or write) with addresses that increment by one on each successive access. When used optimally, this memory port with 32 physical data bits (rd is 32) operating at a clk0 frequency of 133MHz can sustain approximately 1GB/s.

 


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