ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data
Model | Supported |
ADM-XRC | |
ADM-XRC-P | |
ADM-XRC-II-Lite | |
ADM-XRC-II | |
ADM-XPL | ![]() |
ADM-XP | ![]() |
ADP-WRC-II | |
ADP-DRC-II | |
ADP-XPI | |
ADM-XRC-4LX | |
ADM-XRC-4SX | |
ADM-XRC-4FX | |
ADPE-XRC-4FX | |
ADM-XRC-5LX | |
ADM-XRC-5T1 | |
ADM-XRC-5T2 / ADM-XRC-5T2-ADV | |
ADM-XRC-5TZ | |
ADM-XRC-5T-DA1 |
$ADMXRC_SDK4/fpga/verilog/ddma64
The DDMA64 FPGA design demonstrates demand-mode DMA with local bus bursting in 64-bit mode. Data is read from an application buffer in host memory and then simply written back to another application buffer unchanged (a 'loopback' operation). In order to use demand-mode DMA, the host must specify the appropriate mode when performing DMA transfers. This is demonstrated by the DMA sample application.
The design assumes that any DMA transfer on DMA channel 0 is transferring data into the FIFO; hence any direct-slave write where LDACK#[0] is asserted will fill the FIFO with data. Similarly, any DMA transfer on DMA channel 1 is assumed to tbe emptying the FIFO; hence any read where LDACK#[1] is asserted will empty the FIFO of data. The local bus address is ignored during these demand-mode DMA transfers. In other words, the FIFO is visible over the entire FPGA space during demand-mode DMA transfers.
There are two write-only registers that reside in the FPGA direct-slave space. These registers must be written by the host with a DMA transfer count that matches the size of the DMA transfer being performed, prior to the host starting the DMA transfer. Note that these registers cannot be inadvertantly overwritten by demand-mode DMA transfers, as the design qualifies FPGA register accesses using LDACK#[1:0].
Inbound count register (ICOUNT, local bus address 0x0) | |||
Bits | Mnemonic | Type | Function |
1:0 | MBZ | ||
31:2 | N | WO | Inbound DMA transfer count, in 32-bit words |
The inbound count register (ICOUNT) specifies how many words will be transferred in the next DMA transfer in channel 0, in order to transfer data into the FPGA's FIFO. When ICOUNT.N is zero, the FPGA will not assert LDREQ#[0]. The FPGA decrements ICOUNT.N whenever a word of data is transferred on DMA channel 0.
Outbound count register (OCOUNT, local bus address 0x4) | |||
Bits | Mnemonic | Type | Function |
1:0 | MBZ | ||
31:2 | N | WO | Outbound DMA transfer count, in 32-bit words |
The outbound count register (OCOUNT) specifies how many words will be transferred in the next DMA transfer in channel 1, in order to transfer data into the FPGA's FIFO. When OCOUNT.N is zero, the FPGA will not assert LDREQ#[1]. The FPGA decrements OCOUNT.N whenever a word of data is transferred on DMA channel 1.
For a list of the Verilog source files, refer to the appropriate XST project file, as referenced in the following table:
Model | XST script file | XST project file | UCF file |
ADM-XPL | ddma64-xpl-v2p.scr | ddma64-xpl-v2p.prj | ddma64-xpl.ucf |
ADM-XP | ddma64-xp-v2p.scr | ddma64-xp-v2p.prj | ddma64-xp.ucf |
Project Navigator projects can be found in the projnav directory as follows:
Model | Project Navigator project file |
ADM-XPL | projnav/xpl/<device> |
ADM-XP | projnav/xp/<device> |