ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


Clock utility

Model support

Overview

Command-line syntax

Description

FPGA design

Model support

ModelSupported
ADM-XRC
ADM-XRC-P
ADM-XRC-II-Lite
ADM-XRC-II
ADM-XPL
ADM-XP
ADP-WRC-II
ADP-DRC-II
ADP-XPI
ADM-XRC-4LX
ADM-XRC-4SX
ADM-XRC-4FX
ADPE-XRC-4FX
ADM-XRC-5LX
ADM-XRC-5T1
ADM-XRC-5T2
ADM-XRC-5T2-ADV
ADM-XRC-5TZ
ADM-XRC-5T-DA1

Overview

The Clock utility serves two purposes:

Syntax
clock [options ...] [clock input] [frequency]
Options

Option Argument type Meaning
-card base 10 integer ID of card to open
-index base 10 integer Index of card to open
-measure   Disables measurement of approximate frequency.
+measure   Enables measurement of approximate frequency (default)

Description

When run with no arguments, the Clock utility displays a list of clock inputs and their 1-based indices. For example, on an ADM-XRC-5T2 card, running Clock with no arguments produces the following output:

Clock pins available on specified card:

Clock input      Programmable   Clock generator index

1  LCLK          Yes            0
2  MCLKA         Yes            1
3  MCLKB         Yes            1
4  REFCLK        No             N/A
5  XRM_CLKIN     No             N/A
6  XRM_MGTREF    No             N/A
7  PCIE100A      No             N/A

This indicates that of the seven clock inputs, only LCLK (1), MCLKA (2) and MCLKB (3) are programmable. LCLK corresponds to clock generator 0, and MCLKA and MCLKB are copies of the output of clock generator 1.

To measure the frequency of a particular clock input, specify the index of the clock input as the first argument. For example, to measure the local bus clock frequency, run Clock as follows:

clock 1

This produces output in the following form (actual measured values may vary depending on what LCLK frequency has previously been programmed, if any):

Measuring frequency of clock input 1 (LCLK)...
Initial counter value = 625869
Final counter value   = 40624672, delta = 39998803

In this case, the 'delta' value indicates that the frequency of the local bus clock, LCLK, is approximately 40 MHz. Note that since the above command-line only measures the local bus clock frequency (without programming the clock generator), the measured frequency depends upon whatever the current local bus clock frequency happens to be.

The final mode in which Clock can be run both programs a clock generator and measures the resulting frequency. For example, to program the MCLKA/MCLKB clock generator on an ADM-XRC-5T2 card for a frequency of 250 MHz, the following command-line would suffice:

clock 2 250

and this produces output in the following form (actual measured values may vary slightly):

Programming clock generator 1 for 250.00 MHz...
Actual programmed frequency = 250000000.00 Hz
Measuring frequency of clock input 2 (MCLKA)...
Initial counter value = 7709995
Final counter value   = 257703771, delta = 249993776

Here, the 'delta' value indicates that the measured frequency of MCLKA is as expected, approximately 250 MHz.

FPGA Design

This application uses the Clock sample FPGA design (VHDL).

 


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