ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data
A number of sample VHDL FPGA designs are included with the SDK. The purpose of these designs is to demonstrate functionality available on the ADM-XRC series of cards and also to serve as customisable starting points for user-developed applications. The designs are intentionally trivial so that code that implements the functionality being demonstrated can easily be seen.
The sample FPGA designs are used by the sample applications, which demonstrate how software running on the host CPU can interact with an FPGA design.
The table below lists the sample FPGA designs and the sample applications that use them:
Design name | Used by application(s) | Purpose |
Clock | Clock | Measures approximate frequencies at the clock input pins of a reconfigurable computing card. |
DLL | DLL | Demonstrates clock doubling using Virtex DLLs and Virtex-II DCMs |
DDMA | DMA | Demonstrates use of the DMA engines in demand-mode, with bursting on the local bus. |
DDMA64 | DMA | Demonstrates use of the DMA engines in demand-mode, with bursting and 64-bit mode on the local bus. |
FrontIO | FrontIO | A trivial design that walks a '1' bit up the front panel I/O pins. |
ITest | ITest | Sample logic for generating FPGA interrupts. |
Master | Master | Demonstrates how to implement a direct master capability in an FPGA design. |
Memory | Memory | A reference design featuring an interface to the onboard memories that permits access by both the CPU (via a 32-bit local bus) and a processing block within the FPGA. |
Memory64 | Memory | A reference design featuring an interface to the onboard memories that permits access by both the CPU (via a 64-bit local bus) and a processing block within the FPGA. |
RearIO | RearIO | A trivial design that walks a '1' bit up the rear panel I/O pins. |
Simple | Simple | Demonstrates how to implement host-readable registers. |
Simple64 | Simple | Demonstrates how to implement host-readable registers, with 64-bit local bus interface. |
ZBT | Memtest | Demonstrates host access to the ZBT SSRAM. |
ZBT64 | Memtest | Demonstrates host access to the ZBT SSRAM, with 64-bit local bus interface. |