ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


The ddrsdram_timing_t datatype

The ddrsdram_timing_t datatype is exported by the memif package, and is used to specify the timing parameters of an instance of ddrsdram_port.

It is a record type, defined as follows:

type ddrsdram_timing_t is
record
    cas_latency : natural;
    t_refresh   : natural;
    t_mrd       : natural;
    t_dllr      : natural;
    t_rp        : natural;
    t_rfc       : natural;
    t_act       : natural;
    t_wtr       : natural;
    t_rtw       : natural;
    t_rtp       : natural;
    t_wtp       : natural;
    t_ras       : natural;
end record;

This datatype can normally treated as an abstract datatype, since the user application need typically only use one of the predefined constants of type ddrsdram_timing_t. However, should it be necessary to create a new value, the members are defined as follows:

Member Type Function
cas_latency natural CAS latency, in half clock cycles. The only supported value is 5, representing CL2.5.
t_refresh natural Average periodic refresh interval, in clk0 cycles.
t_mrd natural Mode register set command period, in clk0 cycles.
t_dllr natural Minimum number of clk0 cycles between DLL reset deasserted to first memory access.
t_rp natural Minimum number of clk0 cycles between PRE (precharge) and ACT (row activation) or REF (refresh) commands.
t_rfc natural Number of clk0 cycles for completion of a REF (refresh) operation.
t_act natural Minimum number of clk0 cycles between ACT (row activate) and a read or write command.
t_wtr natural Minimum number of clk0 cycles between a write and a read command.
t_rtw natural Minimum number of clk0 cycles between a read and a write command.
t_rtp natural Minimum number of clk0 cycles between a read and a PRE (precharge) command.
t_wtp natural Minimum number of clk0 cycles between a write and a PRE (precharge) command.
t_ras natural Minimum number of clk0 cycles between ACT (row activate) and PRE (precharge) command.

All values in the above table are numbers of clk0 cycles. Thus:

 


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