ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


Local bus sideband signals

The table below lists the sideband signals available to the FPGA on an ADM-XRC series card for special functions such as Demand-mode DMA and interrupt generation.

Note Signal Driven by Description
  FINTI# FPGA FPGA interrupt line

The FINTI# signal allows the FPGA to generate an interrupt on the host. It is negative-edge sensitive. If FINTI# remains asserted after the initial high-to-low transition, further interrupts will cannot be generated until FINTI# transitions high again.
  LDACK# PCI-to-local bus bridge DMA acknowledge

One bit of LDACK# is asserted in a one-hot manner by the PCI-to-local bus bridge at the same time as LADS# in order to indicate that the current burst is a Demand-mode DMA burst. It remains asserted until the end of the burst.

Each bit of LDACK# corresponds to a DMA channel in the PCI-to-local bus bridge. At most one DMA channel may be performing a burst on the local bus at any time; hence at most one bit of LDACK# may be asserted at any time.
  LDREQ# FPGA DMA request

Any bit or all bits of LDREQ# may be asserted by the FPGA to request a Demand-mode DMA burst.

Each bit of LDREQ# corresponds to a DMA channel in the PCI-to-local bus bridge. Provided that the host has started (via the driver) a demand-mode DMA operation on a particular channel, asserting LDREQ# for that DMA channel will eventually result in the DMA engine in the PCI-to-local bus bridge performing a burst with LDACK# for that channel asserted.

While a demand-mode DMA burst is in progress (ie. a bit of LDACK# is asserted), the burst can be terminated by deasserting the corresponding bit of LDREQ#. This is known as "pausing the demand-mode DMA", and will cause the PCI-to-local bus bridge to assert LBLAST# as soon as possible.

When a demand-mode DMA burst has completed and either
  • the PCI-to-local bus bridge has transferred all data in its FIFO, or
  • the demand-mode DMA was paused
then the PCI-to-local bus bridge will not initiate another burst on the local bus for that DMA channel until the corresponding bit of LDREQ# is reasserted.
  LEOT# FPGA End of transfer

This signal may be asserted during a burst that has been initiated by one of the PCI-to-local bus bridge's DMA engines in order to prematurely terminate a DMA transfer (before the requested number of bytes has been transferred). To use LEOT#, a DMA engine must be operating in LEOT mode.

 


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