ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


Clock sample VHDL FPGA design

Model support

Location

Synopsis

FPGA space usage

Source files

Project Navigator files

Modelsim scripts

Model support

ModelSupported
ADM-XRC
ADM-XRC-P
ADM-XRC-II-Lite
ADM-XRC-II
ADM-XPL
ADM-XP
ADP-WRC-II
ADP-DRC-II
ADP-XPI
ADM-XRC-4LX
ADM-XRC-4SX
ADM-XRC-4FX
ADPE-XRC-4FX
ADM-XRC-5LX
ADM-XRC-5T1
ADM-XRC-5T2 / ADM-XRC-5T2-ADV
ADM-XRC-5TZ
ADM-XRC-5T-DA1

Note: the ADM-XRC-5T2-ADV version of this design uses the same source files and bitstreams as the ADM-XRC-5T2, so separate files are not included within this SDK.

Location
$ADMXRC_SDK4/fpga/vhdl/clock
Synopsis

The Clock FPGA design can be used to approximately measure the frequencies of the signals present at the 'standard' clock pins of the target FPGA. It consists of a number of cycle counters that can be read via the local bus interface of the target FPGA.

FPGA Space Usage

The following registers are accessible via the FPGA space:

READ (read count command register, local bus address 0x0)
Bits Mnemonic Type Function
31:0 DO WO/RAX Writing a '1' to a particular bit of this field initiates a read of the corresponding cycle counter.

STATUS (status register, local bus address 0x4)
Bits Mnemonic Type Function
31:0 DONE RO A '1' in a particular bit of this field indicates that either no read command has been issued to the corresponding cycle counter, or that the last read command issues to the corresponding cycle counter has been completed.

COUNT (cycle count registers, local bus addresses 0x80 - 0xFC)

Each 32-bit register in the range 0x80 - 0xFC returns the number of elapsed cycles for the corresponding cycle counter.
Bits Mnemonic Type Function
31:0 N RO Returns the number of cycles that have elapsed for a particular clock input.

To read a cycle counter, the following procedure should be used:

  1. Issue a command to read the cycle counter for the clock input of interest via the READ register. For example, to read the cycle counter for the LCLK input, which is the first cycle counter on all models, write the value 0x00000001 to the READ register.
  2. Poll the STATUS register until the bit corresponding to the clock input of interest returns '1'. This should be the same bit as in step 1 above. For example, when bit 0 of the STATUS register returns '1', the read of the cycle counter corresponding to the LCLK input has been completed.
  3. Read the cycle counter corresponding to the clock input of interest. For the LCLK input, this is the first cycle counter, at local bus address 0x80.

Source files

For a list of the VHDL source files, refer to the appropriate XST project file, as referenced in the following table:

Model XST script file XST project file UCF file
ADM-XRC with Virtex clock-xrc-v.scr clock-xrc-v.prj clock-xrc.ucf
ADM-XRC with Virtex-E clock-xrc-ve.scr clock-xrc-ve.prj clock-xrc.ucf
ADM-XRC-P with Virtex clock-xrcp-v.scr clock-xrcp-v.prj clock-xrcp.ucf
ADM-XRC-P with Virtex-E clock-xrcp-ve.scr clock-xrcp-ve.prj clock-xrcp.ucf
ADM-XRC-II-Lite clock-xrc2l-v2.scr clock-xrc2l-v2.prj clock-xrc2l.ucf
ADM-XRC-II clock-xrc2-v2.scr clock-xrc2-v2.prj clock-xrc2.ucf
ADM-XPL clock-xpl-v2p.scr clock-xpl-v2p.prj clock-xpl.ucf
ADM-XP clock-xp-v2p.scr clock-xp-v2p.prj clock-xp.ucf
ADP-WRC-II clock-wrc2-v2.scr clock-wrc2-v2.prj clock-wrc2.ucf
ADP-DRC-II clock-drc2-v2.scr clock-drc2-v2.prj clock-drc2.ucf
ADP-XPI clock-xpi-v2p.scr clock-xpi-v2p.prj clock-xpi.ucf
ADM-XRC-4LX clock-xrc4lx-v4lx.scr clock-xrc4lx-v4lx.prj clock-xrc4lx.ucf
ADM-XRC-4SX clock-xrc4sx-v4sx.scr clock-xrc4sx-v4sx.prj clock-xrc4sx.ucf
ADM-XRC-4FX with 4VFX100 clock-xrc4fx-v4fx.scr clock-xrc4fx-v4fx.prj clock-xrc4fx-4vfx100.ucf
ADM-XRC-4FX with 4VFX140 clock-xrc4fx-v4fx.scr clock-xrc4fx-v4fx.prj clock-xrc4fx-4vfx140.ucf
ADPE-XRC-4FX with 4VFX100 clock-xrce4fx-v4fx.scr clock-xrce4fx-v4fx.prj clock-xrce4fx-4vfx100.ucf
ADPE-XRC-4FX with 4VFX140 clock-xrce4fx-v4fx.scr clock-xrce4fx-v4fx.prj clock-xrce4fx-4vfx140.ucf
ADM-XRC-5LX clock-xrc5lx-v5lx.scr clock-xrc5lx-v5lx.prj clock-xrc5lx.ucf
ADM-XRC-5T1 with FXT clock-xrc5t1-v5fxt.scr clock-xrc5t1-v5fxt.prj clock-xrc5t1-5vfxt.ucf
ADM-XRC-5T1 with LXT clock-xrc5t1-v5lxt.scr clock-xrc5t1-v5lxt.prj clock-xrc5t1.ucf
ADM-XRC-5T1 with SXT clock-xrc5t1-v5sxt.scr clock-xrc5t1-v5sxt.prj clock-xrc5t1.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with 5VFX100T clock-xrc5t2-v5fxt.scr clock-xrc5t2-v5fxt.prj clock-xrc5t2-5vfx100t.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with 5VFX130T clock-xrc5t2-v5fxt.scr clock-xrc5t2-v5fxt.prj clock-xrc5t2-5vfx130t.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with 5VFX200T clock-xrc5t2-v5fxt.scr clock-xrc5t2-v5fxt.prj clock-xrc5t2-5vfx200t.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with 5VLX110T, 5VLX155T or 5VLX220T clock-xrc5t2-v5lxt.scr clock-xrc5t2-v5lxt.prj clock-xrc5t2-5vlx110t.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with 5VLX330T clock-xrc5t2-v5lxt.scr clock-xrc5t2-v5lxt.prj clock-xrc5t2-5vlx330t.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with 5VSX240T clock-xrc5t2-v5sxt.scr clock-xrc5t2-v5sxt.prj clock-xrc5t2-5vsx240t.ucf
ADM-XRC-5TZ with 5VFX100T clock-xrc5tz-v5fxt.scr clock-xrc5tz-v5fxt.prj clock-xrc5tz-5vfx100t.ucf
ADM-XRC-5TZ with 5VFX130T clock-xrc5tz-v5fxt.scr clock-xrc5tz-v5fxt.prj clock-xrc5tz-5vfx130t.ucf
ADM-XRC-5TZ with 5VFX200T clock-xrc5tz-v5fxt.scr clock-xrc5tz-v5fxt.prj clock-xrc5tz-5vfx200t.ucf
ADM-XRC-5TZ with 5VLX110T, 5VLX155T or 5VLX220T clock-xrc5tz-v5lxt.scr clock-xrc5tz-v5lxt.prj clock-xrc5tz-5vlx110t.ucf
ADM-XRC-5TZ with 5VLX330T clock-xrc5tz-v5lxt.scr clock-xrc5tz-v5lxt.prj clock-xrc5tz-5vlx330t.ucf
ADM-XRC-5TZ with 5VSX240T clock-xrc5tz-v5sxt.scr clock-xrc5tz-v5sxt.prj clock-xrc5tz-5vsx240t.ucf
ADM-XRC-5T-DA1 with FXT clock-xrc5tda1-v5fxt.scr clock-xrc5tda1-v5fxt.prj clock-xrc5tda1-5vfxt.ucf
ADM-XRC-5T-DA1 with LXT clock-xrc5tda1-v5lxt.scr clock-xrc5tda1-v5lxt.prj clock-xrc5tda1.ucf
ADM-XRC-5T-DA1 with SXT clock-xrc5tda1-v5sxt.scr clock-xrc5tda1-v5sxt.prj clock-xrc5tda1.ucf

Project Navigator files

Project Navigator projects can be found in the projnav directory as follows:

Model Project Navigator project file
ADM-XRC projnav/xrc/<device>
ADM-XRC-P projnav/xrcp/<device>
ADM-XRC-II-Lite projnav/xrc2l/<device>
ADM-XRC-II projnav/xrc2/<device>
ADM-XPL projnav/xpl/<device>
ADM-XP projnav/xp/<device>
ADP-WRC-II projnav/wrc2/<device>
ADP-DRC-II projnav/drc2/<device>
ADP-XPI projnav/xpi/<device>
ADM-XRC-4LX projnav/xrc4lx/<device>
ADM-XRC-4SX projnav/xrc4sx/<device>
ADM-XRC-4FX projnav/xrc4fx/<device>
ADPE-XRC-4FX projnav/xrce4fx/<device>
ADM-XRC-5LX projnav/xrc5lx/<device>
ADM-XRC-5T1 projnav/xrc5t1/<device>
ADM-XRC-5T2
ADM-XRC-5T2-ADV
projnav/xrc5t2/<device>
ADM-XRC-5TZ projnav/xrc5tz/<device>
ADM-XRC-5T-DA1 projnav/xrc5tda1/<device>

Modelsim scripts

Example Modelsim-compatible script files for simulating this design are provided. Refer to the following table for the appropriate command line for a particular model:

Model Shell command
ADM-XRC vsim -do "do clock-xrc.do"
ADM-XRC-P vsim -do "do clock-xrc.do"
ADM-XRC-II-Lite vsim -do "do clock-xrc.do"
ADM-XRC-II vsim -do "do clock-xrc.do"
ADM-XPL vsim -do "do clock-xpl.do"
ADM-XP vsim -do "do clock-xpl.do"
ADP-WRC-II vsim -do "do clock-wrc2.do"
ADP-DRC-II vsim -do "do clock-drc2.do"
ADP-XPI vsim -do "do clock-xpi.do"
ADM-XRC-4LX vsim -do "do clock-xrc4lx.do"
ADM-XRC-4SX vsim -do "do clock-xrc4lx.do"
ADM-XRC-4FX vsim -do "do clock-xrc4fx.do"
ADPE-XRC-4FX vsim -do "do clock-xrce4fx.do"
ADM-XRC-5LX vsim -do "do clock-xrc5lx.do"
ADM-XRC-5T1 vsim -do "do clock-xrc5t1.do"
ADM-XRC-5T2
ADM-XRC-5T2-ADV
vsim -do "do clock-xrc5t1.do"
ADM-XRC-5TZ vsim -do "do clock-xrc5t1.do"
ADM-XRC-5T-DA1 vsim -do "do clock-xrc5tda1.do"

 


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