ADM-XRC SDK 2.8.1 User Guide (Linux)
© Copyright 2001-2009 Alpha Data


DDMA64 sample VHDL FPGA design

Model support

Location

Synopsis

FPGA space usage

Source files

Project Navigator files

Modelsim scripts

Model support

ModelSupported
ADM-XRC 
ADM-XRC-P 
ADM-XRC-II-Lite 
ADM-XRC-II 
ADM-XPL 2VP20, 2VP30 only
ADM-XP
ADP-WRC-II 
ADP-DRC-II 
ADP-XPI
ADM-XRC-4LX 
ADM-XRC-4SX 
ADM-XRC-4FX
ADPE-XRC-4FX
ADM-XRC-5LX
ADM-XRC-5T1
ADM-XRC-5T2 / ADM-XRC-5T2-ADV
ADM-XRC-5TZ 
ADM-XRC-5T-DA1 

Note: the ADM-XRC-5T2-ADV version of this design uses the same source files and bitstreams as the ADM-XRC-5T2, so separate files are not included within this SDK.

Location
$ADMXRC_SDK4/fpga/vhdl/ddma64
Synopsis

The DDMA64 FPGA design demonstrates demand-mode DMA with local bus bursting in 64-bit mode. Data is read from an application buffer in host memory and then simply written back to another application buffer unchanged (a 'loopback' operation). In order to use demand-mode DMA, the host must specify the appropriate mode when performing DMA transfers. This is demonstrated by the DMA sample application.

FPGA Space Usage

The design assumes that any DMA transfer on DMA channel 0 is transferring data into the FIFO; hence any direct-slave write where LDACK#[0] is asserted will write data into the FIFO. Similarly, any DMA transfer on DMA channel 1 is assumed to be reading data out of the FIFO; hence any read where LDACK#[1] is asserted will remove data from the FIFO. The local bus address is ignored during these demand-mode DMA transfers. In other words, the FIFO is visible over the entire FPGA space during demand-mode DMA transfers.

There are registers that reside in the FPGA direct-slave space. These registers must be written by the host with a DMA transfer count that matches the size of the DMA transfer being performed, prior to the host starting the DMA transfer. Note that these registers cannot be inadvertantly overwritten by demand-mode DMA transfers, as the design qualifies FPGA register accesses using LDACK#[1:0].

Inbound count register (ICOUNT, local bus address 0x0)
Bits Mnemonic Type Function
2:0   MBZ  
31:3 N WO Inbound DMA transfer count, in 64-bit words

The inbound count register (ICOUNT) specifies how many words will be transferred in the next DMA transfer in channel 0, in order to transfer data into the FPGA's FIFO. When ICOUNT.N is zero, the FPGA will not assert LDREQ#[0]. The FPGA decrements ICOUNT.N whenever a word of data is transferred on DMA channel 0.

Outbound count register (OCOUNT, local bus address 0x4)
Bits Mnemonic Type Function
2:0   MBZ  
31:3 N WO Outbound DMA transfer count, in 64-bit words

The outbound count register (OCOUNT) specifies how many words will be transferred in the next DMA transfer in channel 1, in order to transfer data into the FPGA's FIFO. When OCOUNT.N is zero, the FPGA will not assert LDREQ#[1]. The FPGA decrements OCOUNT.N whenever a word of data is transferred on DMA channel 1.

Source files

For a list of the VHDL source files, refer to the appropriate XST project file, as referenced in the following table:

Model XST script file XST project file UCF file
ADM-XPL ddma64-xpl-v2p.scr ddma64-xpl-v2p.prj ddma64-xpl.ucf
ADM-XP ddma64-xp-v2p.scr ddma64-xp-v2p.prj ddma64-xp.ucf
ADP-XPI ddma64-xpi-v2p.scr ddma64-xpi-v2p.prj ddma64-xpi.ucf
ADM-XRC-4FX with 4vfx100 ddma64-xrc4fx-v4fx.scr ddma64-xrc4fx-v4fx.prj ddma64-xrc4fx-4vfx100.ucf
ADM-XRC-4FX with 4vfx140 ddma64-xrc4fx-v4fx.scr ddma64-xrc4fx-v4fx.prj ddma64-xrc4fx-4vfx140.ucf
ADPE-XRC-4FX with 4VFX100 ddma64-xrce4fx-v4fx.scr ddma64-xrce4fx-v4fx.prj ddma64-xrce4fx-4vfx100.ucf
ADPE-XRC-4FX with 4VFX140 ddma64-xrce4fx-v4fx.scr ddma64-xrce4fx-v4fx.prj ddma64-xrce4fx-4vfx140.ucf
ADM-XRC-5LX ddma64-xrc5lx-v5lx.scr ddma64-xrc5lx-v5lx.prj ddma64-xrc5lx.ucf
ADM-XRC-5T1 with FXT ddma64-xrc5t1-v5fxt.scr ddma64-xrc5t1-v5fxt.prj ddma64-xrc5t1-5vfxt.ucf
ADM-XRC-5T1 with LXT ddma64-xrc5t1-v5lxt.scr ddma64-xrc5t1-v5lxt.prj ddma64-xrc5t1.ucf
ADM-XRC-5T1 with SXT ddma64-xrc5t1-v5sxt.scr ddma64-xrc5t1-v5sxt.prj ddma64-xrc5t1.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with FXT ddma64-xrc5t2-v5fxt.scr ddma64-xrc5t2-v5fxt.prj ddma64-xrc5t2-5vfxt.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with LXT ddma64-xrc5t2-v5lxt.scr ddma64-xrc5t2-v5lxt.prj ddma64-xrc5t2.ucf
ADM-XRC-5T2 or ADM-XRC-5T2-ADV with SXT ddma64-xrc5t2-v5sxt.scr ddma64-xrc5t2-v5sxt.prj ddma64-xrc5t2.ucf

Project Navigator files

Project Navigator projects can be found in the projnav directory as follows:

Model Project Navigator project file
ADM-XPL projnav/xpl/<device>
ADM-XP projnav/xp/<device>
ADP-XPI projnav/xpi/<device>
ADM-XRC-4FX projnav/xrc4fx/<device>
ADPE-XRC-4FX projnav/xrce4fx/<device>
ADM-XRC-5LX projnav/xrc5lx/<device>
ADM-XRC-5T1 projnav/xrc5t1/<device>
ADM-XRC-5T2
ADM-XRC-5T2-ADV
projnav/xrc5t2/<device>

Modelsim scripts

Example Modelsim-compatible script files for simulating this design are provided. Refer to the following table for the appropriate command line for a particular model:

Model Shell command
ADM-XPL vsim -do "do ddma64-xpl.do"
ADM-XP vsim -do "do ddma64-xpl.do"
ADP-XPI vsim -do "do ddma64-xpi.do"
ADM-XRC-4FX vsim -do "do ddma64-xrc4fx.do"
ADPE-XRC-4FX vsim -do "do ddma64-xrce4fx.do"
ADM-XRC-5LX vsim -do "do ddma64-xrc5.do"
ADM-XRC-5T1 vsim -do "do ddma64-xrc5.do"
ADM-XRC-5T2
ADM-XRC-5T2-ADV
vsim -do "do ddma64-xrc5.do"

 


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